Hi all,
I'm using STM32F429BIT6。
my question is: C3 is 3.3uF±10%，How do you like this circuit?When WDG reset in the MCU STM32F429BIT6,It will lead to CMOS failure of the MCU NRST？If C3 is 2.2uF±10%，the CMOS of the MCU NRST will be OK？Thanks！
1 ACCEPTED SOLUTION
Accepted Solutions
Dear @Zhang2024 ,
as exchanged above by @TDK @KnarfB , there is something very important for Reset pin as you see in the picture ( there is 2 arrow) that mean the pin is bidirectional . So if an internal Software reset or by a watchdog is propagated externally first and then to see the real reset and / sampled it should go back ( VIL of reset reached ) . Adding a high capacitor or external pull-pull will make it not seen and so never trigger. You need to compte the total new RC time versus the guaranteed VIL level of reset pin .
Hope it helps ,
STOne-32
It will be fine, but the recommendation is to remove R5 since there is an internal pullup, and change C3 to a 0.1 uF.
dm00115714-getting-started-with-stm32f4xxxx-mcu-hardware-development-stmicroelectronics.pdf
Dear @Zhang2024 ,
as exchanged above by @TDK @KnarfB , there is something very important for Reset pin as you see in the picture ( there is 2 arrow) that mean the pin is bidirectional . So if an internal Software reset or by a watchdog is propagated externally first and then to see the real reset and / sampled it should go back ( VIL of reset reached ) . Adding a high capacitor or external pull-pull will make it not seen and so never trigger. You need to compte the total new RC time versus the guaranteed VIL level of reset pin .
Hope it helps ,
STOne-32
