I'm trying to get a continuous GPDMA transfers from ADC4 into a buffer on a Nucleo-U5A5 board. I'm not using any security settings.
It seems that the ADC conversion are working correctly. When debugging I can poll the DR and see the values change (4 potentiometers). Examining the HAL DMA channel struct always show a Locked/Busy state. List state is busy as well. I assume that's expected for a continuously running transfer?
My only problem is that the buffer I assigned for the transfer is not getting updated.
Are there any SRAM location limitations for DMA transfers on the U5A5? I've seen some references to it on other devices. Any other gotchas with GPDMA on the U5A5?
