Sorry, good question:
you configure SPI as 9bit Word Size, and you write to a 16bit FIFO (sound already like a "discrepancy", at least an issue to bear in mind).
Does it mean, every FIFO write will take just a 9bit word from it? (I am not sure - STM guys?)
Or: does it take 16bits (as 9 + 7bits) and waits for another word written for the remaining 11bits still missing? (another FIFO write needed)
I have never used 9bit Word Size (DATASIZE), to be honest. It is an unclear question for me as well:
"how is the 16bit FIFO taken to send 9bit words?"
Worst case: you have to shuffle the bits, because: 9bit words on a 16bit FIFO is never aligned. Maybe you have to "shuffle" bits so that you send 9 + 7 bits but on next word the remaining 2 + 9 + 5 bits and so on (maybe with dummy bits at the last FIFO write).
No idea how the 16bit FIFO "maps" to send 9bit words, and if it would end up and send (writing to FIFO) an "incomplete word", just to provide the remaining bits (and where to place the "remaining bits", potentially on LSB part?)
You could try: reshuffle the bits and assume: a 16bit FIFO will really result in shifting out 16bits. Do not assume as: writing 9bits via a 16bit word will just transmit 9bit (because Word Size is set to 9bit and FIFO entry should ignore 7bits).
Why do you need a 9bit word?
What happens on a scope?
Do you see that (N-1) x 9bits come out, just the last few bits are missing?
What is your waveform (compared to the expected bit transmission)?
If so, you might consider that FIFO as 16bit - sends 16bits via SPI. If you assume to provide for every 16bit FIFO entry just 9bits (because word size is 9bits) - but it fails - the assumption is potentially wrong.
Try to send the "smallest dominator", e.g. 9 x 16bits = 144bits which is now a "full complete set of bits" (matching with the 16bit FIFO entries).
I would assume: 16bit FIFO entries means 16bit out (not just 9 bits and ignoring bits written to FIFO). You can try different "assumptions" and see with a scope what happens.
I am sure, the SPI counts the number of bits to send, but with 9bit word size and 16bit FIFO there is a chance that just one FIFO entry is missing (at the end).
Check via scope what comes out (and what and how many bits are missing). If you miss bits on a scope - the EOT will not come (because SPI misses these bits as well).
