STM32L4P5G-DK: User Manual UM2651 available?

[Andreas Bolsch]

STM32L4P5G-DK data brief refers to the UM mentioned above for detailed description. But this manual doesn't seem to be available.

Any clues where to find it???

[waclawek.jan]

Hi Andreas,

I don't know the answer, but do you actually have this Disco? If yes, what display do you use/intend to use with it?

Maybe care to comment?

https://community.st.com/s/question/0D53W000002eMaFSAU/stm32l4p5gdk

Thanks,

Jan

@Raouf​ 

[Andreas Bolsch]

Yes, I do have this board, but I don't need any display, it's only intended for further development of http://openocd.zylin.com/#/c/4321/

Currently limited success, only single/dual SPI and QPI modes work ... Octo mode seems to suffer from silicon bug? Whereas on L4R9 it works even in octo mode without any real issue, on L4P5 and H7B3 indirect read mode doesn't seem to work at all. Still looking for a workaround ...

[waclawek.jan]

Thanks for the info and good luck with the project.

I was not aware of openOCD supporting external memories, except the VisualGDB's initiative, but they took a different approach - plugins.

JW

[Imen GH · Accepted solution]

​Hello @Andreas Bolsch​ 

The user manual is now available on our website

Please see this link

Best  Regards,

[Andreas Bolsch]

Thanks!

[Raouf]

Hi Andreas,

The STM32L4P5/L4Q5 and STM32H7B3/H7A3 have a new OctoSPI controller version which is working well.

Can you please state which are the issues you are facing? Do you interfacing an external Octal FLASH, PSRAM or other... ?

Thanks !

[Tesla DeLorean]

Was hoping to get the STM32L4P5G-DK boards in today, but looks like FedEx will get them to me on Monday.

Need to spin up the NUCLEO-H7A3ZI, and L4P5 should be here next week some time. Will let you know how the QSPI/OSPI looks

[Raouf]

​Yes please :)

Thanks !!

[Andreas Bolsch]

Thanks for your inquiry. This issue appears in indirect read mode for MX25LM51245G with "mixed" settings, i.e. instruction and data both DTR but data STR with DQS enabled (as required for RSDR, RDCR, RDID, ... commands). The flash's datasheet specifies 4 dummy clocks.

On L4R9 (STM32L4R9I-Disco) this setting works fine, as do more dummy clocks (apparently the DQS logic is armed even before all dummy clocks have elapsed).

However, on L4P5 (STM32L4P5G-Disco), when setting 4 dummy clocks, the command never completes, no data at all available in FIFO,

in SR BUSY sticks at '1', FLEVEL remains at 0. With 5 or more dummy clocks, all data is retrieved properly, no "shifted" data due to extra dummy cycles. So the number of dummy cycles is actually a "don't care" as long as at least 5 are specified?

The RM says in 19.4.3 "Dummy-cycles phase ... It is recommended to have at least five dummy cycles when using memories with DQS activated.", which appears to be quite misleading. And the description strongly suggests that the given number of dummy cycles is always present, which is obviously not the case when DQS handling is enabled.

And in 19.6.15 "OCTOSPI_TCR ... DCYC[4:0]: Number of dummy cycles

This field defines the duration of the dummy phase. In both SDR and DTR modes, it specifies a number of CLK cycles (0-31).

It is recommended to have at least six dummy cycles when using memories with DQS activated."

ES0510 - Rev 2 doesn't give any restriction on the number of dummy cycles when using DQS.

The debug output for L4R9 vs. L4P5 is attached. The flash had been set to DTR OPI mode via WRCR2 before. Other relevant settings:

0x01190100            ;# OCTOSPI_DCR1: MTYP=0x1, FSIZE=0x19, CSHT=0x01, CKMODE=0

0x00000001            ;# OCTOSPI_DCR2: PRESCALER=1

The same problem appears on STM32H7B3I-Disco, and can be fixed by spcecifying 5 or more dummy clocks as well.

(Woudn't be surprised to find this on STM32L562-Disco as well, but the export restrictions ...).

Apart from this point you're certainly right, the octospi seems to work quite well in simple SPI, QPI mode, single or dual flash, regardless of operating mode, and OPI in memory mapped mode.