STM32L476xx disambiguation

[Noyb]

Posted on May 18, 2016 at 15:53The original post was too long to process during our migration. Please click on the attachment to read the original post.

[Tesla DeLorean]

Posted on May 18, 2016 at 17:04

These are things you'd perhaps want to discuss with the FAE assigned to your project, this is primarily a user forum, and not one the IC designers, software engineers or technical writers service.

[Noyb]

Posted on May 18, 2016 at 17:24

Nope, no FAE or whatever you call it assigned to my project. Using publicly available document and material, obviously not in final revision. Btw...

Case 4 (CCMR3) : Solved (between OR1 and CCR5) Case 21 : stm32l476xx.h, l520 FMC_Bank1_TypeDef, BTCR register This register is not described into the documentation and the header file. Case 22 : stm32l476xx.h, l529 FMC_Bank1E_TypeDef, BWTR register stm32l476xx.h, l4372 /******************  Bit definition for FMC_BWTRx registers (x=1..4)  *********/ en.DM00083560.pdf, p379 Bit 14 EXTMOD: Extended mode enable This register is not described into the documentation. Case 23 : en.DM00083560.pdf, p440 ADDIS=1 disables the ADC and disable the ADC. ADEN and ADDIS are then automatically cleared by hardware as soon as the analog ADC is effectively disabled. disables the ADC and disable the ADC ... Case 24 : en.DM00083560.pdf, p440 Once DEEPPWD=0 and ADVREGRN=1, the ADC can be enabled and the ADC... The register ADVREGRN is not described into the documentation. Do you mean ADVREGEN ? Case 25 : en.DM00083560.pdf, p436 The software must wait for the startup time of the ADC voltage regulator (TADCVREG_STUP, =20us) before launching a calibration or enabling the ADC. en.DM00083560.pdf, p440 ...the ADC can be enabled and the ADC needs a stabilization time of tSTAB (DAC, not ADC, =5 us) before it starts converting accurately... So, which tempo is correct ? Case 26 : en.DM00083560.pdf, p45 Table 56. FMC_BCRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355 Table 57. FMC_BTRx bit fields. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356 Table 58. FMC_BCRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358 Table 59. FMC_BTRx bit fields. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358 Table 60. FMC_BWTRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359 Table 61. FMC_BCRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361 Table 62. FMC_BTRx bit fields. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361 Table 63. FMC_BWTRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362 Table 64. FMC_BCRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363 Table 65. FMC_BTRx bit fields. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364 Table 66. FMC_BWTRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364 Table 67. FMC_BCRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366 Table 68. FMC_BTRx bit fields. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366 Table 69. FMC_BWTRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367 Table 70. FMC_BCRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368 Table 71. FMC_BTRx bit fields. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369 Table 72. FMC_BCRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374 Table 73. FMC_BTRx bit fields. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375 Table 74. FMC_BCRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376 Table 75. FMC_BTRx bit fields. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377 Seriously, can't you sum it up in a table with rows and columns for better comparison ?

[Tesla DeLorean]

Posted on May 18, 2016 at 19:52

Ok, just saying, because I don't think this is going to get much attention/traction in this venue.

I'll point out that the USB stuff has historically used Third Party IP (

http://www.synopsys.com/IP/InterfaceIP/USB/Pages/default.aspx

), and there are likely NDAs around register level documentation with that.

[Tesla DeLorean]

Posted on May 18, 2016 at 19:57

FAE - Field Application Engineer

Working either for the distributor of your parts (Arrow, Farnell, etc) or ST

[Noyb]

Posted on May 19, 2016 at 11:08

Case 27 :

stm32l476xx.h, l332   __IO uint8_t  IDR;         /*!< CRC Independent data register,               Address offset: 0x04 */ en.DM00083560.pdf, p340 Bits 31:0 IDR[31:0]: General-purpose 32-bit data register bits So, 8 bits or 32 bits ? Get your facts straight, for God's sake !

[waclawek.jan]

Posted on May 19, 2016 at 11:27

IMO it's more useful to refer to DS/RM by its number and revision, rather than filename.

Thus, in RM0351 rev.1, CRC_IDR was indeed quoted to be 8-bit. Probably an omission corrected in DS, not in the header. It's a shame the key header(s) is(are) in such a state. Mayla, Syrine or anybody other of ST listening here, could you please push this as a Cube issue? I presume it gets higher priority than general rants these days. I'd also like to reiterate my request to add bitfield-value constants/defines to these headers. JW

[Walid FTITI_O]

Posted on May 19, 2016 at 15:49

Hi Noyb,

Thanks for your contribution and feedbacks. Some of them are relevant and other ones are not (see example below). Like:

Case 5 :

stm32l476xx.h, l1053 USB_OTG_GlobalTypeDef, HNPTXSTS register en.DM00083560.pdf, p1541 43.15.11 OTG non-periodic transmit FIFO/queue status register (OTG_HNPTXSTS) in stm32l476xx.h, it is written : /*!<  Non Periodic Tx FIFO/Queue Sts reg           02Ch*/ -> It is OK. I will report relevant ones internally for check. -Hannibal-

[Walid FTITI_O]

Posted on May 19, 2016 at 15:51

Hi waclawek.jan,

''I'd also like to reiterate my request to add bitfield-value constants/defines to these headers'' Can you give us a refresh about this request ( any reference thread for example) ? -Hannibal-

[Walid FTITI_O]

Posted on May 19, 2016 at 16:34

Hi Noyb, 

An answer to your question in one of the irrelevant feedbacks (case 25):

Case 25 :

en.DM00083560.pdf, p436 The software must wait for the startup time of the ADC voltage regulator (TADCVREG_STUP, =20us) before launching a calibration or enabling the ADC. en.DM00083560.pdf, p440 ...the ADC can be enabled and the ADC needs a stabilization time of tSTAB (DAC, not ADC, =5 us) before it starts converting accurately... So, which tempo is correct ? -> You can figure out the difference from reference manual :

''(T

ADCVREG_STUP

) before launching a calibration or enabling the ADC. This delay must be implemented by software''. -> delay (ADC voltage regulator statup time) before you can enable the ADC or launch

calibration

.

''the ADC can be enabled and the ADC needs a stabilization time of t

STAB

before it starts converting accurately'' -> delay after enabling ADC and before starting conversion -Hannibal-