STM32L476 minimal ADC sampling time

[Uwe Bonnes]

Hello,

STM32L476 data sheet Rev 8 talks in 3.15 about "Down to 18.75 ns sampling time" while table 77 only lists a minimal 31.25 ns minimal sampling time. Is 18.75 ns sampling time possible and with what setting?

[InsignificantBit]

The 31.25 ns is indeed the shortest sampling time possible. The mention of 18.75 ns in the datasheet is indeed an error.

My previous reply was incorrect. I apologize for any inconvenience.

18.75 ns sampling time is possible, the 31.25 ns is the lowest time for which we provide some specifications in the datasheet.

[Uwe Bonnes]

How is it possible? SMPR registers have no published setting for a single sampling cycle. Or do you mean to overclock the CPU by 250 %.

[KDJEM.1 · Accepted solution]

Hello @Uwe Bonnes ,

Thank you for bringing this issue to our attention.

After checking internally with @InsignificantBit "18.75 ns sampling time" isn't correct.

The minimum sampling time is calculated as follows:

2.5 cycles / 80 MHz (max ADC frequency) = 31.25ns

So table 77 is correct, but this sentence “Down to 18.75 ns sampling time" is not correct.

Internal ticket number: 170685 (This is an internal tracking number and is not accessible or usable by customers).

Thank you.

Kaouthar