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STM32G474 ADC channel voltage bleed

lliwdliw
Associate

Hi

I've noticed unexpected behaviour with the ADCs on the STM32G474RE.

The behaviour I have found, is that voltage from one channel can bleed onto the next sampled channel .eg  if channel 1 has a high voltage, and channel 2 is at 0V, I see a large ADC count present when I sample ADC channel 2, this can be as high as 300 counts (12-bit mode). this can happen from channel 1->2, 2->3, or even 3->1 sample taken from next timer triggered conversion at 30kHz. The signals are driven directly from a buffer, so low impedance, limited capacitance on the traces.

Settings

ADC input clock - 160MHz

prescaler = 4 (ADC clock 40MHz)

Regular conversion enabled - 4 conversions

external trigger conversion set to TIM1 Out event - timer @30kHz

channel sample time - 2.5Cycles + 12.5 conversion overhead

I have used an STMF412RET for a similar application, and we do not see the voltage bleed between channels.

The only solution I have found so far is to increase the minimal sample time of the ADC from 2.5 samples to 12.5, this is a little disappointing, as it has limiting effects on the application.

Do you have any suggestions as to what we can do to increase the speed of our ADC sample rate

Many Thanks

Will

The graphs below show reading 4 ADC channels 1, 2, 3 are at 0V, and channel 4 is at 3V. I varied the ADC sample rate from 2.5, 12.5, 24.5 and 47.5. Only at 47.5 did I see no interference from the high voltage channel. I have less evidence, but I believe this also has an effect in the opposite direction causing high voltage readings to be reduced if sampled after a low voltage.

In the example below, I am sampling 4 difference channels, but would see the same issue if I sampled channel 1 three times, and channel 4 once

lliwdliw_0-1689856914151.png

lliwdliw_1-1689856946072.png

lliwdliw_2-1689856977926.png

lliwdliw_3-1689857004318.png

note, the sample number is the additional samples above the 12.5 sample overhead of the ADC

 

 



5 REPLIES 5
TDK
Guru

In AN2834, See "Reference voltage decoupling and impedance" and potentially "Injection current effect" for explanations for this effect why it's more pronounced in one direction.

2.5 cycles/sample is crazy fast and you're going to need a solid layout to get the best accuracy.

https://www.st.com/resource/en/application_note/an2834-how-to-get-the-best-adc-accuracy-in-stm32-microcontrollers-stmicroelectronics.pdf

If you feel a post has answered your question, please click "Accept as Solution".
MasterT
Senior III

Post schematic of your buffer, and what is the Reference voltage in use? 

> 2.5 cycles/sample is crazy fast

+1. Refer to the datasheet for required maximum impedance of the input signal source. Don't forget, that VSSA (AGND) forms vital part of the circuit, and that VREF+ has to be rock solid, too.

Also read AN5346.

JW

RomainR.
ST Employee

Hello @lliwdliw 

You are using ADC outside the max frequency recommendations.
As you can see in DS12288 Table 66 below:

fADC Max = 60MHz.

RomainR_0-1689861423380.png

BR

Romain,

To give better visibility on the answered topics, please click on Accept as Solution on the reply which solved your issue or answered your question.

ADC clock 160/4 = 40 MHz is OK

At 40 MHz 2.5 clock are 0.0625µs. For a step of 3.3V from one channel to the next this is a slew rate of 53V/µs.

To charge a capacitor of 5pf.

Are you sure your buffer has such a slew rate? Check the internal output resistance of the buffer...