STM32L431: Does fast flash programming only work for bank erase?

[DHase.1]

The STM32L431 RM is ambiguous about being able to use fast flash programming with page erase.

In the paragraph on Fast Programming the RM first refers to pages--

"This mode allows to program a row (32 double word) and to reduce the page programming ..."

But for the program steps it refers to banks--

"1. Perform a mass erase of the bank to program."

Can the fast programming be used when erasing and writing page-by-page, or can it only be used when a mass erase is used?

The "note" also indicates that the code to run the fast programming cannot be in the same bank being flashed, so I presume that for the L431 some code in sram would be required to load a row and test the busy.

[Piranha]

Indeed ST should clarify that point about the necessity of mass erase.

Also noticed a copy-paste error.

RM0394 Rev 4, section "3.3.7 Flash main memory programming sequences", page 85:

Fast programming

The Flash main memory programming sequence in standard mode is as follows:

[DHase.1]

Here is another statement where I think "full zero" is intended to mean 0xffffffff rather than 0x00000000--

"3.3.7

Flash main memory programming sequences

Programming in a previously programmed address is not allowed except if the data to write

is full zero, and any attempt will set PROGERR flag..."

[Piranha]

No, it actually means 0x0000000000000000. That is an additional feature, which allows invalidating of the previously programmed memory. Therefore the FLASH on those devices has kind of a 3 functional states:

1. Erased, 0xFFFFFFFFFFFFFFFF.
2. Programmed, any value.
3. Invalidated, 0x0000000000000000.

[DHase.1]

Piranha,

Thanks for the clarification. The notion of three states really helps with the understanding. Rereading the RM (for the nth time) I see how that way of viewing it is embedding in the RM description.

Interesting to ponder various situations, especially with regard to a set of calibrations that one might want to update. How might a program determine which double words have not been programmed. I suppose if double read from flash was all F's and that was a value never permitted one could tag it as a writable double. Or, if zero was not permitted, the program could search down to the first non-zero, and instead some page erase/write, one sets old values to zero.

Another puzzling result I ran into is that load double/store double (standard mode) was producing a single double word error (the double word appeared not be flashed) about 1 out 10 pages. No noticeable pattern. By changing to two load word/store word I have not seen an error. One guess is that due to some race-time the hardware tries to store high word before the low word. For the two load & stores, the HAL routine places an ISB instruction between the first and second word load & stores, so I presume "they" had some insight into what was going on with the hardware.