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STM32H7B0RBT6 with QSPI PSRAM APS6404L-3SQR

Forum|Forum|2 years ago
October 5, 2023
5 replies
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Hi Community,

During a project we are using the microcontroller STM32H7B0RBT6 with QSPI PSRAM APS6404L-3SQR , it works fine in indirect mode either in quad read and quad write, but the issue is with the write in memory mapped mode when trying to write less than 8 byte, one for example (*((uint8_t*) (0x90000010))=0x55;) the 7 others bytes are zeroed it seems that the write accept only 8 bytes if the data is less than 8 the other bytes are zeroed as you can see :

instead written 8 bytes (*((uint64_t*) (0x90000010))=0xA5A5A5A5A5A5A5A5ULL;) works fine !!

Did someone face a similar problem could please provide some suggestions to do, thanks,

Here I share the code that I have used to enable the memory mapped mode

OSPI_MemoryMappedTypeDef sMemMappedCfg = {0};
OSPI_RegularCmdTypeDef sCommand = {0};

/* set command to write to qspi ram */

sCommand.OperationType = HAL_OSPI_OPTYPE_WRITE_CFG;
sCommand.FlashId = HAL_OSPI_FLASH_ID_1;
sCommand.InstructionMode = HAL_OSPI_INSTRUCTION_4_LINES;
sCommand.InstructionSize = HAL_OSPI_INSTRUCTION_8_BITS;
sCommand.InstructionDtrMode = HAL_OSPI_INSTRUCTION_DTR_DISABLE;
sCommand.AddressMode = HAL_OSPI_ADDRESS_4_LINES;
sCommand.AddressSize = HAL_OSPI_ADDRESS_24_BITS;
sCommand.AddressDtrMode = HAL_OSPI_ADDRESS_DTR_DISABLE;
sCommand.AlternateBytesMode = HAL_OSPI_ALTERNATE_BYTES_NONE;
sCommand.DataMode = HAL_OSPI_DATA_4_LINES;
sCommand.DataDtrMode = HAL_OSPI_DATA_DTR_DISABLE;
sCommand.DQSMode = HAL_OSPI_DQS_ENABLE; /* Memory-mapped write error response when DQS output is disabled */
sCommand.SIOOMode = HAL_OSPI_SIOO_INST_EVERY_CMD;
sCommand.Instruction = QUAD_WRITE_DATA_CMD;
sCommand.Address = 0;
sCommand.NbData = 0;
sCommand.DummyCycles = 0;

if (HAL_OSPI_Command(&hospi1, &sCommand, HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)

{

Error_Handler();

}

/* set command to read from spi ram */

sCommand.DQSMode = HAL_OSPI_DQS_DISABLE;
sCommand.OperationType = HAL_OSPI_OPTYPE_READ_CFG;
sCommand.Instruction = FAST_READ_QUAD_DATA_CMD;
sCommand.DummyCycles = 6;

if (HAL_OSPI_Command(&hospi1, &sCommand, HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)

{

Error_Handler();

}

/* set up memory mapping */

/* release nCS after access, else no refresh */
sMemMappedCfg.TimeOutActivation = HAL_OSPI_TIMEOUT_COUNTER_ENABLE;
sMemMappedCfg.TimeOutPeriod = 1;

if (HAL_OSPI_MemoryMapped(&hospi1, &sMemMappedCfg) != HAL_OK)

{

Error_Handler();

}

QSPI

Best answer by ALAMI_Othmane

This memory require a specific refresh value that resolve the issue, now it's working fine and stable with the memory mapped mode, we have actually used as a heap for our application contain the frame buffer and all others data

to make it work, you need to:
- Configure the MPU for the specific mapped addresses area

- Pay attention to the refresh value ( should equal 241) when initializing the octospi interface to have better stability for values stored in this ram

Tesla DeLorean

Guru

Same team? https://community.st.com/t5/stm32-mcus-products/stm32h7b0-aps6404l-3sqr-issue-with-write-in-memory-mapped-mode/m-p/596139#M224462

Check MPU configurations for this region.

@Alex - APMemory

https://community.st.com/t5/stm32-mcus-products/using-quad-spi-psram-with-a-stm32-h7-is-that-possible-and-wise/td-p/152161

Tips, Buy me a coffee, or three.. PayPal Venmo (See Profile) Up vote any posts that you find helpful, it shows what's working..

A

ALAMI_OthmaneAuthor

Associate II

MPU is reconfigured to :

MPU_InitStruct.Enable = MPU_REGION_ENABLE;

MPU_InitStruct.Number = MPU_REGION_NUMBER5;

MPU_InitStruct.BaseAddress = 0x90000000;

MPU_InitStruct.Size = MPU_REGION_SIZE_8MB;

MPU_InitStruct.SubRegionDisable = 0x0;

MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL1;

MPU_InitStruct.AccessPermission = MPU_REGION_FULL_ACCESS;

MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_ENABLE;

MPU_InitStruct.IsShareable = MPU_ACCESS_NOT_SHAREABLE;

MPU_InitStruct.IsCacheable = MPU_ACCESS_CACHEABLE;

MPU_InitStruct.IsBufferable = MPU_ACCESS_NOT_BUFFERABLE;

this handle this issue and we can now do software write in one byte, but the issue is still exist when you write by debugger .

KDJEM.1

ST Technical Moderator

Hello @ALAMI_Othmane,

First let me thank you for posting.

A similar question is posted here.

There is an errata "Memory-mapped write error response when DQS output is disabled". So with this errata we need to enable the DQS when doing memory mapped writes even if the memory do not support DQS. This is the workaround as you did.

So when you do a 8-16-32 bit write , the OCTOSPI will output 64-bit and mask the rest using DQS pin. The problem is if the memory do not support DQS (which is in our case), the rest of the AXI data will be written to the memory. so if you write : (*((uint8_t*) (0x90000000))=0x55;) 0x90000000 will be written correctly but the data from address 0x90000001-0x90000007 will be corrupted.

Kaouthar

To give better visibility on the answered topics, please click on "Best answer" on the reply which solved your issue or answered your question.

A

ALAMI_OthmaneAuthor

Associate II

Hello KDJEM.1

Thanks for your answer,

So you confirm there is no way to write less than 8 bytes with memory mapped mode activated,

We need this info cause this memory will be used as heap in a project where we will allocate different sizes of Data .

Best Regards

Alex - APMemory

Associate II

Hi,

There is a Memory Mapped Write limitation with QSPI SDR on STMH7A/B. If possible you might want to consider OPI PSRAM (11 pin instead of 6, but up to x4 bandwith). The OPI version of APS6404L-3SQR is APS6408L-3OBM-BA (3V also available in 128Mb APS12808L-3OBM- BA)

Alex

A

ALAMI_OthmaneAuthor

Associate II

Hi Alex,

Thanks for your Answer,

For the specific version of MCU used there is no OPI, do you confirm we can't allocate the heap in this QSPI memory ?

Best,

Othmane

Alex - APMemory

Associate II

Hi,

This MCU is supporting Octal PSRAM (x2), or do you mean it's not available on your board ?

If you wish to stay with lowest pincount, QSPI DDR is also supported, such as APS12808O-DQ-WA

With QSPI SDR, Memory mapped write is not supported

Alex

A

ALAMI_OthmaneAuthorBest answer

Associate II

This memory require a specific refresh value that resolve the issue, now it's working fine and stable with the memory mapped mode, we have actually used as a heap for our application contain the frame buffer and all others data

to make it work, you need to:
- Configure the MPU for the specific mapped addresses area

- Pay attention to the refresh value ( should equal 241) when initializing the octospi interface to have better stability for values stored in this ram

Zhou JianQiang

Senior

Hi ：

Can you share the settings of MPU with me(it will be better if you can give the source code)?

I want to use memory map with this IC too.

Alex - APMemory

Associate II

Hi,

which memory PN are you looking for ?

Let me just remind that STM32H7B0 supports OPI (APS6408L)... and QSPI DDR (APS12808O-DQ) full spec but have a memory mapped write limitation for QSPI SDR (APS6404L...)

Thanks

Alex

PS: Overview of IoT RAM (QSPI, OPI & HPI PSRAM) support

STM32 MCU family	HPI/OPI	OPI	QSPI SDR	QSPI DDR	Comment
STM32L4Rx	-	✓*	-	-	*avoid odd address write issue - ADMUX recommended
STM32L5 STM32L4P5/Q5 STM32U575/585 STM32H5	-	✓	✓	✓
STM32H7A3/B3 STM32H72x/3x	-	✓	✓*	✓	* doesn't support QSPI SDR Memory mapped Write mode
STM32U59x/U5Ax, STM32U5Fx/U5Gx STM32H7Rx/Sx	✓	✓	✓	✓
All STM32 supporting NOR QSPI	-	-	✓*	-	* doesn't support QSPI SDR Memory mapped Write mode
APMemory device	256Mb~512Mb 1.8V BGA24/WLCSP APS256XXN-OBR/OB9-... APS512XXN-OBR/OB9-...	64Mb~512Mb 1.8V ~3V BGA24/WLCSP APS6408L-xOBM-... APS12808L-xOBM-BA APS12808O-OBR-WB APS25608N-OBR-BD APS51208N-OBR-BD	16Mb~128Mb 1.8V ~3V SOP8/USON8/WLCSP APS1604M-xSQR-… APS6404L-xSQR-... APS12808O-SQRH-WA	128Mb 1.8V WLCSP APS12808O-DQ-WA

S

SMazu.3

Associate III

can you give me the the source file pls?

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