Previously, I used the HAL_DFSDM_FilterRegularStart_DMA method to enable each of the eight filters one by one. The result was a 2.4Mhz clock output, exactly as configured in CubeMX.
Now, to achieve high sync between 8 filters, i referred to the synchronization content in the reference manual(RM0455):
i followed the instruction and programmed as below:
/**
* @brief Configurate DFSDM Filter
* @retval None
*/
void WJ_DFSDM_FilterSyncConfig(void)
{
// Disable Filter to set RSYNC
hdfsdm1_filter0.Instance->FLTCR1 &= ~DFSDM_FLTCR1_DFEN;
hdfsdm1_filter1.Instance->FLTCR1 &= ~DFSDM_FLTCR1_DFEN;
hdfsdm1_filter2.Instance->FLTCR1 &= ~DFSDM_FLTCR1_DFEN;
hdfsdm1_filter3.Instance->FLTCR1 &= ~DFSDM_FLTCR1_DFEN;
hdfsdm1_filter4.Instance->FLTCR1 &= ~DFSDM_FLTCR1_DFEN;
hdfsdm1_filter5.Instance->FLTCR1 &= ~DFSDM_FLTCR1_DFEN;
hdfsdm1_filter6.Instance->FLTCR1 &= ~DFSDM_FLTCR1_DFEN;
hdfsdm1_filter7.Instance->FLTCR1 &= ~DFSDM_FLTCR1_DFEN;
// Set all 7 RSYNC (let alone filter0）
hdfsdm1_filter1.Instance->FLTCR1 |= DFSDM_FLTCR1_RSYNC;
hdfsdm1_filter2.Instance->FLTCR1 |= DFSDM_FLTCR1_RSYNC;
hdfsdm1_filter3.Instance->FLTCR1 |= DFSDM_FLTCR1_RSYNC;
hdfsdm1_filter4.Instance->FLTCR1 |= DFSDM_FLTCR1_RSYNC;
hdfsdm1_filter5.Instance->FLTCR1 |= DFSDM_FLTCR1_RSYNC;
hdfsdm1_filter6.Instance->FLTCR1 |= DFSDM_FLTCR1_RSYNC;
hdfsdm1_filter7.Instance->FLTCR1 |= DFSDM_FLTCR1_RSYNC;
}Then i configurate DFSDM buffer in DMA mode:
/**
* @brief Start DFSDM Convertion
* @retval None
*/
void WJ_DFSDM_FilterSyncStart(void)
{
// Enable all 8 filters
hdfsdm1_filter0.Instance->FLTCR1 |= DFSDM_FLTCR1_DFEN;
hdfsdm1_filter1.Instance->FLTCR1 |= DFSDM_FLTCR1_DFEN;
hdfsdm1_filter2.Instance->FLTCR1 |= DFSDM_FLTCR1_DFEN;
hdfsdm1_filter3.Instance->FLTCR1 |= DFSDM_FLTCR1_DFEN;
hdfsdm1_filter4.Instance->FLTCR1 |= DFSDM_FLTCR1_DFEN;
hdfsdm1_filter5.Instance->FLTCR1 |= DFSDM_FLTCR1_DFEN;
hdfsdm1_filter6.Instance->FLTCR1 |= DFSDM_FLTCR1_DFEN;
hdfsdm1_filter7.Instance->FLTCR1 |= DFSDM_FLTCR1_DFEN;
// Config DMA buffer in DMA mode
if (HAL_OK != HAL_DFSDM_FilterRegularStart_DMA(&hdfsdm1_filter0, aRecBuff0, AUDIO_BUFFER_SIZE)) {
Error_Handler();
}
if (HAL_OK != HAL_DFSDM_FilterRegularStart_DMA(&hdfsdm1_filter1, aRecBuff1, AUDIO_BUFFER_SIZE)) {
Error_Handler();
}
if (HAL_OK != HAL_DFSDM_FilterRegularStart_DMA(&hdfsdm1_filter2, aRecBuff2, AUDIO_BUFFER_SIZE)) {
Error_Handler();
}
if (HAL_OK != HAL_DFSDM_FilterRegularStart_DMA(&hdfsdm1_filter3, aRecBuff3, AUDIO_BUFFER_SIZE)) {
Error_Handler();
}
if (HAL_OK != HAL_DFSDM_FilterRegularStart_DMA(&hdfsdm1_filter4, aRecBuff4, AUDIO_BUFFER_SIZE)) {
Error_Handler();
}
if (HAL_OK != HAL_DFSDM_FilterRegularStart_DMA(&hdfsdm1_filter5, aRecBuff5, AUDIO_BUFFER_SIZE)) {
Error_Handler();
}
if (HAL_OK != HAL_DFSDM_FilterRegularStart_DMA(&hdfsdm1_filter6, aRecBuff6, AUDIO_BUFFER_SIZE)) {
Error_Handler();
}
if (HAL_OK != HAL_DFSDM_FilterRegularStart_DMA(&hdfsdm1_filter7, aRecBuff7, AUDIO_BUFFER_SIZE)) {
Error_Handler();
}
}then i started Convertion:
hdfsdm1_filter0.Instance->FLTCR1 |= DFSDM_FLTCR1_RSWSTART;However, when I checked the CLK output, I found that the clock frequency changed to about 3Mhz, varying from 2.6Mhz to 3.0Mhz. See below:
So I tried to debug. When the program ran through DFSDM1_Init(), the 3Mhz clock output emerged, but the waveform was abnormal. Also, after the program ran through WJ_DFSDM_FilterSyncConfig(), WJ_DFSDM_FilterSyncStart(), and hdfsdm1_filter0.Instance->FLTCR1 |= DFSDM_FLTCR1_RSWSTART, the CLK output did not change.
Although it can normally enter the DMA transfer interrupt, this abnormal CLK output indicates a problem. I want to know how to correctly configure the registers to achieve the synchronization of DFSDM1 filter1 - 7 with filter0 as described in the reference manual. Why does the current configuration lead to an abnormal clock waveform? Are there any overlooked details or configurations?
Appended is my DFSDM1_Init():
static void MX_DFSDM1_Init(void)
{
/* USER CODE BEGIN DFSDM1_Init 0 */
/* USER CODE END DFSDM1_Init 0 */
/* USER CODE BEGIN DFSDM1_Init 1 */
/* USER CODE END DFSDM1_Init 1 */
hdfsdm1_filter0.Instance = DFSDM1_Filter0;
hdfsdm1_filter0.Init.RegularParam.Trigger = DFSDM_FILTER_SW_TRIGGER;
hdfsdm1_filter0.Init.RegularParam.FastMode = ENABLE;
hdfsdm1_filter0.Init.RegularParam.DmaMode = ENABLE;
hdfsdm1_filter0.Init.FilterParam.SincOrder = DFSDM_FILTER_SINC4_ORDER;
hdfsdm1_filter0.Init.FilterParam.Oversampling = 128;
hdfsdm1_filter0.Init.FilterParam.IntOversampling = 1;
if (HAL_DFSDM_FilterInit(&hdfsdm1_filter0) != HAL_OK)
{
Error_Handler();
}
hdfsdm1_filter1.Instance = DFSDM1_Filter1;
hdfsdm1_filter1.Init.RegularParam.Trigger = DFSDM_FILTER_SW_TRIGGER;
hdfsdm1_filter1.Init.RegularParam.FastMode = ENABLE;
hdfsdm1_filter1.Init.RegularParam.DmaMode = ENABLE;
hdfsdm1_filter1.Init.FilterParam.SincOrder = DFSDM_FILTER_SINC4_ORDER;
hdfsdm1_filter1.Init.FilterParam.Oversampling = 128;
hdfsdm1_filter1.Init.FilterParam.IntOversampling = 1;
if (HAL_DFSDM_FilterInit(&hdfsdm1_filter1) != HAL_OK)
{
Error_Handler();
}
hdfsdm1_filter2.Instance = DFSDM1_Filter2;
hdfsdm1_filter2.Init.RegularParam.Trigger = DFSDM_FILTER_SW_TRIGGER;
hdfsdm1_filter2.Init.RegularParam.FastMode = ENABLE;
hdfsdm1_filter2.Init.RegularParam.DmaMode = ENABLE;
hdfsdm1_filter2.Init.FilterParam.SincOrder = DFSDM_FILTER_SINC4_ORDER;
hdfsdm1_filter2.Init.FilterParam.Oversampling = 128;
hdfsdm1_filter2.Init.FilterParam.IntOversampling = 1;
if (HAL_DFSDM_FilterInit(&hdfsdm1_filter2) != HAL_OK)
{
Error_Handler();
}
hdfsdm1_filter3.Instance = DFSDM1_Filter3;
hdfsdm1_filter3.Init.RegularParam.Trigger = DFSDM_FILTER_SW_TRIGGER;
hdfsdm1_filter3.Init.RegularParam.FastMode = ENABLE;
hdfsdm1_filter3.Init.RegularParam.DmaMode = ENABLE;
hdfsdm1_filter3.Init.FilterParam.SincOrder = DFSDM_FILTER_SINC4_ORDER;
hdfsdm1_filter3.Init.FilterParam.Oversampling = 128;
hdfsdm1_filter3.Init.FilterParam.IntOversampling = 1;
if (HAL_DFSDM_FilterInit(&hdfsdm1_filter3) != HAL_OK)
{
Error_Handler();
}
hdfsdm1_filter4.Instance = DFSDM1_Filter4;
hdfsdm1_filter4.Init.RegularParam.Trigger = DFSDM_FILTER_SW_TRIGGER;
hdfsdm1_filter4.Init.RegularParam.FastMode = ENABLE;
hdfsdm1_filter4.Init.RegularParam.DmaMode = ENABLE;
hdfsdm1_filter4.Init.FilterParam.SincOrder = DFSDM_FILTER_SINC4_ORDER;
hdfsdm1_filter4.Init.FilterParam.Oversampling = 128;
hdfsdm1_filter4.Init.FilterParam.IntOversampling = 1;
if (HAL_DFSDM_FilterInit(&hdfsdm1_filter4) != HAL_OK)
{
Error_Handler();
}
hdfsdm1_filter5.Instance = DFSDM1_Filter5;
hdfsdm1_filter5.Init.RegularParam.Trigger = DFSDM_FILTER_SW_TRIGGER;
hdfsdm1_filter5.Init.RegularParam.FastMode = ENABLE;
hdfsdm1_filter5.Init.RegularParam.DmaMode = ENABLE;
hdfsdm1_filter5.Init.FilterParam.SincOrder = DFSDM_FILTER_SINC4_ORDER;
hdfsdm1_filter5.Init.FilterParam.Oversampling = 128;
hdfsdm1_filter5.Init.FilterParam.IntOversampling = 1;
if (HAL_DFSDM_FilterInit(&hdfsdm1_filter5) != HAL_OK)
{
Error_Handler();
}
hdfsdm1_filter6.Instance = DFSDM1_Filter6;
hdfsdm1_filter6.Init.RegularParam.Trigger = DFSDM_FILTER_SW_TRIGGER;
hdfsdm1_filter6.Init.RegularParam.FastMode = ENABLE;
hdfsdm1_filter6.Init.RegularParam.DmaMode = ENABLE;
hdfsdm1_filter6.Init.FilterParam.SincOrder = DFSDM_FILTER_SINC4_ORDER;
hdfsdm1_filter6.Init.FilterParam.Oversampling = 128;
hdfsdm1_filter6.Init.FilterParam.IntOversampling = 1;
if (HAL_DFSDM_FilterInit(&hdfsdm1_filter6) != HAL_OK)
{
Error_Handler();
}
hdfsdm1_filter7.Instance = DFSDM1_Filter7;
hdfsdm1_filter7.Init.RegularParam.Trigger = DFSDM_FILTER_SW_TRIGGER;
hdfsdm1_filter7.Init.RegularParam.FastMode = ENABLE;
hdfsdm1_filter7.Init.RegularParam.DmaMode = ENABLE;
hdfsdm1_filter7.Init.FilterParam.SincOrder = DFSDM_FILTER_SINC4_ORDER;
hdfsdm1_filter7.Init.FilterParam.Oversampling = 128;
hdfsdm1_filter7.Init.FilterParam.IntOversampling = 1;
if (HAL_DFSDM_FilterInit(&hdfsdm1_filter7) != HAL_OK)
{
Error_Handler();
}
hdfsdm1_channel0.Instance = DFSDM1_Channel0;
hdfsdm1_channel0.Init.OutputClock.Activation = ENABLE;
hdfsdm1_channel0.Init.OutputClock.Selection = DFSDM_CHANNEL_OUTPUT_CLOCK_AUDIO;
hdfsdm1_channel0.Init.OutputClock.Divider = 2;
hdfsdm1_channel0.Init.Input.Multiplexer = DFSDM_CHANNEL_EXTERNAL_INPUTS;
hdfsdm1_channel0.Init.Input.DataPacking = DFSDM_CHANNEL_STANDARD_MODE;
hdfsdm1_channel0.Init.Input.Pins = DFSDM_CHANNEL_SAME_CHANNEL_PINS;
hdfsdm1_channel0.Init.SerialInterface.Type = DFSDM_CHANNEL_SPI_RISING;
hdfsdm1_channel0.Init.SerialInterface.SpiClock = DFSDM_CHANNEL_SPI_CLOCK_INTERNAL;
hdfsdm1_channel0.Init.Awd.FilterOrder = DFSDM_CHANNEL_FASTSINC_ORDER;
hdfsdm1_channel0.Init.Awd.Oversampling = 1;
hdfsdm1_channel0.Init.Offset = 0;
hdfsdm1_channel0.Init.RightBitShift = 0x05;
if (HAL_DFSDM_ChannelInit(&hdfsdm1_channel0) != HAL_OK)
{
Error_Handler();
}
hdfsdm1_channel1.Instance = DFSDM1_Channel1;
hdfsdm1_channel1.Init.OutputClock.Activation = ENABLE;
hdfsdm1_channel1.Init.OutputClock.Selection = DFSDM_CHANNEL_OUTPUT_CLOCK_AUDIO;
hdfsdm1_channel1.Init.OutputClock.Divider = 2;
hdfsdm1_channel1.Init.Input.Multiplexer = DFSDM_CHANNEL_EXTERNAL_INPUTS;
hdfsdm1_channel1.Init.Input.DataPacking = DFSDM_CHANNEL_STANDARD_MODE;
hdfsdm1_channel1.Init.Input.Pins = DFSDM_CHANNEL_SAME_CHANNEL_PINS;
hdfsdm1_channel1.Init.SerialInterface.Type = DFSDM_CHANNEL_SPI_RISING;
hdfsdm1_channel1.Init.SerialInterface.SpiClock = DFSDM_CHANNEL_SPI_CLOCK_INTERNAL;
hdfsdm1_channel1.Init.Awd.FilterOrder = DFSDM_CHANNEL_FASTSINC_ORDER;
hdfsdm1_channel1.Init.Awd.Oversampling = 1;
hdfsdm1_channel1.Init.Offset = 0;
hdfsdm1_channel1.Init.RightBitShift = 0x05;
if (HAL_DFSDM_ChannelInit(&hdfsdm1_channel1) != HAL_OK)
{
Error_Handler();
}
hdfsdm1_channel2.Instance = DFSDM1_Channel2;
hdfsdm1_channel2.Init.OutputClock.Activation = ENABLE;
hdfsdm1_channel2.Init.OutputClock.Selection = DFSDM_CHANNEL_OUTPUT_CLOCK_AUDIO;
hdfsdm1_channel2.Init.OutputClock.Divider = 2;
hdfsdm1_channel2.Init.Input.Multiplexer = DFSDM_CHANNEL_EXTERNAL_INPUTS;
hdfsdm1_channel2.Init.Input.DataPacking = DFSDM_CHANNEL_STANDARD_MODE;
hdfsdm1_channel2.Init.Input.Pins = DFSDM_CHANNEL_SAME_CHANNEL_PINS;
hdfsdm1_channel2.Init.SerialInterface.Type = DFSDM_CHANNEL_SPI_RISING;
hdfsdm1_channel2.Init.SerialInterface.SpiClock = DFSDM_CHANNEL_SPI_CLOCK_INTERNAL;
hdfsdm1_channel2.Init.Awd.FilterOrder = DFSDM_CHANNEL_FASTSINC_ORDER;
hdfsdm1_channel2.Init.Awd.Oversampling = 1;
hdfsdm1_channel2.Init.Offset = 0;
hdfsdm1_channel2.Init.RightBitShift = 0x05;
if (HAL_DFSDM_ChannelInit(&hdfsdm1_channel2) != HAL_OK)
{
Error_Handler();
}
hdfsdm1_channel3.Instance = DFSDM1_Channel3;
hdfsdm1_channel3.Init.OutputClock.Activation = ENABLE;
hdfsdm1_channel3.Init.OutputClock.Selection = DFSDM_CHANNEL_OUTPUT_CLOCK_AUDIO;
hdfsdm1_channel3.Init.OutputClock.Divider = 2;
hdfsdm1_channel3.Init.Input.Multiplexer = DFSDM_CHANNEL_EXTERNAL_INPUTS;
hdfsdm1_channel3.Init.Input.DataPacking = DFSDM_CHANNEL_STANDARD_MODE;
hdfsdm1_channel3.Init.Input.Pins = DFSDM_CHANNEL_SAME_CHANNEL_PINS;
hdfsdm1_channel3.Init.SerialInterface.Type = DFSDM_CHANNEL_SPI_RISING;
hdfsdm1_channel3.Init.SerialInterface.SpiClock = DFSDM_CHANNEL_SPI_CLOCK_INTERNAL;
hdfsdm1_channel3.Init.Awd.FilterOrder = DFSDM_CHANNEL_FASTSINC_ORDER;
hdfsdm1_channel3.Init.Awd.Oversampling = 1;
hdfsdm1_channel3.Init.Offset = 0;
hdfsdm1_channel3.Init.RightBitShift = 0x05;
if (HAL_DFSDM_ChannelInit(&hdfsdm1_channel3) != HAL_OK)
{
Error_Handler();
}
hdfsdm1_channel4.Instance = DFSDM1_Channel4;
hdfsdm1_channel4.Init.OutputClock.Activation = ENABLE;
hdfsdm1_channel4.Init.OutputClock.Selection = DFSDM_CHANNEL_OUTPUT_CLOCK_AUDIO;
hdfsdm1_channel4.Init.OutputClock.Divider = 2;
hdfsdm1_channel4.Init.Input.Multiplexer = DFSDM_CHANNEL_EXTERNAL_INPUTS;
hdfsdm1_channel4.Init.Input.DataPacking = DFSDM_CHANNEL_STANDARD_MODE;
hdfsdm1_channel4.Init.Input.Pins = DFSDM_CHANNEL_SAME_CHANNEL_PINS;
hdfsdm1_channel4.Init.SerialInterface.Type = DFSDM_CHANNEL_SPI_RISING;
hdfsdm1_channel4.Init.SerialInterface.SpiClock = DFSDM_CHANNEL_SPI_CLOCK_INTERNAL;
hdfsdm1_channel4.Init.Awd.FilterOrder = DFSDM_CHANNEL_FASTSINC_ORDER;
hdfsdm1_channel4.Init.Awd.Oversampling = 1;
hdfsdm1_channel4.Init.Offset = 0;
hdfsdm1_channel4.Init.RightBitShift = 0x05;
if (HAL_DFSDM_ChannelInit(&hdfsdm1_channel4) != HAL_OK)
{
Error_Handler();
}
hdfsdm1_channel5.Instance = DFSDM1_Channel5;
hdfsdm1_channel5.Init.OutputClock.Activation = ENABLE;
hdfsdm1_channel5.Init.OutputClock.Selection = DFSDM_CHANNEL_OUTPUT_CLOCK_AUDIO;
hdfsdm1_channel5.Init.OutputClock.Divider = 2;
hdfsdm1_channel5.Init.Input.Multiplexer = DFSDM_CHANNEL_EXTERNAL_INPUTS;
hdfsdm1_channel5.Init.Input.DataPacking = DFSDM_CHANNEL_STANDARD_MODE;
hdfsdm1_channel5.Init.Input.Pins = DFSDM_CHANNEL_SAME_CHANNEL_PINS;
hdfsdm1_channel5.Init.SerialInterface.Type = DFSDM_CHANNEL_SPI_RISING;
hdfsdm1_channel5.Init.SerialInterface.SpiClock = DFSDM_CHANNEL_SPI_CLOCK_INTERNAL;
hdfsdm1_channel5.Init.Awd.FilterOrder = DFSDM_CHANNEL_FASTSINC_ORDER;
hdfsdm1_channel5.Init.Awd.Oversampling = 1;
hdfsdm1_channel5.Init.Offset = 0;
hdfsdm1_channel5.Init.RightBitShift = 0x05;
if (HAL_DFSDM_ChannelInit(&hdfsdm1_channel5) != HAL_OK)
{
Error_Handler();
}
hdfsdm1_channel6.Instance = DFSDM1_Channel6;
hdfsdm1_channel6.Init.OutputClock.Activation = ENABLE;
hdfsdm1_channel6.Init.OutputClock.Selection = DFSDM_CHANNEL_OUTPUT_CLOCK_AUDIO;
hdfsdm1_channel6.Init.OutputClock.Divider = 2;
hdfsdm1_channel6.Init.Input.Multiplexer = DFSDM_CHANNEL_EXTERNAL_INPUTS;
hdfsdm1_channel6.Init.Input.DataPacking = DFSDM_CHANNEL_STANDARD_MODE;
hdfsdm1_channel6.Init.Input.Pins = DFSDM_CHANNEL_SAME_CHANNEL_PINS;
hdfsdm1_channel6.Init.SerialInterface.Type = DFSDM_CHANNEL_SPI_RISING;
hdfsdm1_channel6.Init.SerialInterface.SpiClock = DFSDM_CHANNEL_SPI_CLOCK_INTERNAL;
hdfsdm1_channel6.Init.Awd.FilterOrder = DFSDM_CHANNEL_FASTSINC_ORDER;
hdfsdm1_channel6.Init.Awd.Oversampling = 1;
hdfsdm1_channel6.Init.Offset = 0;
hdfsdm1_channel6.Init.RightBitShift = 0x05;
if (HAL_DFSDM_ChannelInit(&hdfsdm1_channel6) != HAL_OK)
{
Error_Handler();
}
hdfsdm1_channel7.Instance = DFSDM1_Channel7;
hdfsdm1_channel7.Init.OutputClock.Activation = ENABLE;
hdfsdm1_channel7.Init.OutputClock.Selection = DFSDM_CHANNEL_OUTPUT_CLOCK_AUDIO;
hdfsdm1_channel7.Init.OutputClock.Divider = 2;
hdfsdm1_channel7.Init.Input.Multiplexer = DFSDM_CHANNEL_EXTERNAL_INPUTS;
hdfsdm1_channel7.Init.Input.DataPacking = DFSDM_CHANNEL_STANDARD_MODE;
hdfsdm1_channel7.Init.Input.Pins = DFSDM_CHANNEL_SAME_CHANNEL_PINS;
hdfsdm1_channel7.Init.SerialInterface.Type = DFSDM_CHANNEL_SPI_RISING;
hdfsdm1_channel7.Init.SerialInterface.SpiClock = DFSDM_CHANNEL_SPI_CLOCK_INTERNAL;
hdfsdm1_channel7.Init.Awd.FilterOrder = DFSDM_CHANNEL_FASTSINC_ORDER;
hdfsdm1_channel7.Init.Awd.Oversampling = 1;
hdfsdm1_channel7.Init.Offset = 0;
hdfsdm1_channel7.Init.RightBitShift = 0x05;
if (HAL_DFSDM_ChannelInit(&hdfsdm1_channel7) != HAL_OK)
{
Error_Handler();
}
if (HAL_DFSDM_FilterConfigRegChannel(&hdfsdm1_filter0, DFSDM_CHANNEL_0, DFSDM_CONTINUOUS_CONV_ON) != HAL_OK)
{
Error_Handler();
}
if (HAL_DFSDM_FilterConfigRegChannel(&hdfsdm1_filter1, DFSDM_CHANNEL_1, DFSDM_CONTINUOUS_CONV_ON) != HAL_OK)
{
Error_Handler();
}
if (HAL_DFSDM_FilterConfigRegChannel(&hdfsdm1_filter2, DFSDM_CHANNEL_2, DFSDM_CONTINUOUS_CONV_ON) != HAL_OK)
{
Error_Handler();
}
if (HAL_DFSDM_FilterConfigRegChannel(&hdfsdm1_filter3, DFSDM_CHANNEL_3, DFSDM_CONTINUOUS_CONV_ON) != HAL_OK)
{
Error_Handler();
}
if (HAL_DFSDM_FilterConfigRegChannel(&hdfsdm1_filter4, DFSDM_CHANNEL_4, DFSDM_CONTINUOUS_CONV_ON) != HAL_OK)
{
Error_Handler();
}
if (HAL_DFSDM_FilterConfigRegChannel(&hdfsdm1_filter5, DFSDM_CHANNEL_5, DFSDM_CONTINUOUS_CONV_ON) != HAL_OK)
{
Error_Handler();
}
if (HAL_DFSDM_FilterConfigRegChannel(&hdfsdm1_filter6, DFSDM_CHANNEL_6, DFSDM_CONTINUOUS_CONV_ON) != HAL_OK)
{
Error_Handler();
}
if (HAL_DFSDM_FilterConfigRegChannel(&hdfsdm1_filter7, DFSDM_CHANNEL_7, DFSDM_CONTINUOUS_CONV_ON) != HAL_OK)
{
Error_Handler();
}
/* USER CODE BEGIN DFSDM1_Init 2 */
/* USER CODE END DFSDM1_Init 2 */
}
