Hi,
The STM32H7RSxx TRM specifies, for ETH_MACMDIOAR, the following CSR values:
Bits 11:8 CR[3:0]: CSR Clock Range
The CSR Clock Range selection determines the frequency of the MDC clock according to
the CSR clock frequency (eth_hclk):
0000: MDC clock = eth_hclk / 42
0001: MDC clock = eth_hclk / 62
0010: MDC clock = eth_hclk / 16
0011: MDC clock = eth_hclk / 26
0100: MDC clock = eth_hclk / 102
0101: MDC clock = eth_hclk / 124
0110 to 0111: Reserved, must not be used
The suggested range of CSR clock frequency applicable for each value (when Bit 11 = 0) ensures that the MDC clock is approximately between 1.0 MHz to 2.5 MHz frequency range.
When Bit 11 is set, you can achieve a higher frequency of the MDC clock than the frequency limit of 2.5 MHz (specified in the IEEE 802.3) and program a clock divider of lower value.
For example, when CSR clock is of 100 MHz frequency and you program these bits to 1010, the resultant MDC clock is of 12.5 MHz which is above the range specified in IEEE 802.3. Program the following values only if the interfacing chips support faster MDC clocks:
1000: eth_hclk / 4
1001: eth_hclk / 6
1010: eth_hclk / 8
1011: eth_hclk / 10
1100: eth_hclk / 12
1101: eth_hclk / 14
1110: eth_hclk / 16
1111: eth_hclk / 18
Value 2 (0010) and 14 (1110) are repeated for eth_hclk / 16.
Also, there is a jump from eth_hclk/64 to eth_hclk /16, then to eth_hclk/26 and then to eth_hclk/102.
These seems strange values and jumps..
Is it possible that might be some error?
Could someone clarify?
Thanks,
s.
