STM32H7A3xI/G ADC frequency limitation

[Neiluj]

I am not sure I properly understand the STM32H7A3xI/G ADC frequency limitation

In the DEV13195 - Rev8 - Datasheet, section 6.3.21 16-bit ADC characteristics, table 93 ADC characteristics, page 143

It says the fADC max frequency is 50 MHz with boost mode activated

This specification seems to match the one ine the section 6.3.1 General operating conditions, Table 23. Maximum allowed clock frequencies, page 84

where it also says that fadc_ker_ck maximum value is 50 Mhz

And the same clock fadc_ker_ck is describe at the final adc clock in the RM0455 - Rev 11 - Reference manual, 27.4.3 ADC clocks, Figure 158. ADC Clock scheme, page 931

Based on this I understand the limitation only apply to final frequency fadc_ker_ck, and it is possible to use for exemple a system clock adc_sclk of 200 MHz, divide it by 4 via the Bits PRESC[3:0] of ADCx_CCR, and select it via the Bits CKMODE[1:0] of ADCx_CCR, since the clock is also
divided by two at the end, the fadc_ker_ck would be 25 MHz which is in the allowed range (< 50MHz)

Is my comprehension correct ? because when using the ioc configurator just to check this configuration it does not work if the source frequency adc_sclk or adc_ker_ck_input is above 50MHz, either the synchonous mode selection is grayed out or the clock is in red in the clock configurator (see attached captures)

[AScha.3]

The  fadc_ker_ck maximum value is 50 Mhz , for boost11 ->

So whats your boost setting ?

I have (on H743) ->

and

and boost ->

and dont forget: (on some chip revisions different limits!)

[Neiluj]

According to the documentation the BOOST mode is not related to the voltage scale in DEV13195 - Rev8 - Datasheet, section 6.3.1 General operating conditions, Table 23. Maximum allowed clock frequencies, page 84 the max frequency for fadc_ker_ck is 50 MHz for VOS0 to VOS3

The Boost mode is selected in via the bits BOOST[1:0] in the ADC_CR register of ADC  RM0455 - Rev 11 - Reference manual, 27.6.3 ADC control register (ADC_CR), page 1015

The boost mode selection is done at the end of the HAL_ADC_Init() function based on the selected source clock for the ADC.

It seems there is a limitation in the ioc editor for adc_sclk or adc_ker_ck_input, because if I use divider to set adc_sclk below 50 MHz, I am able to select synchonous mode selection, which is no longer grayed out in the adc clock source, and if i manually input 50 for the adc_ker_ck_input in the clock editor it is no more in error.

Actually I won't use the editor no more, and I want to use only HAL library, but I want to be sure to be able to use an adc_sclk source for ADC above 50 MHz but with the clock dividers the final fadc_ker_ck will be below 50 MHz

[AScha.3]

>but I want to be sure to be able to use an adc_sclk source for ADC above 50 MHz 

Why ?

+

>Actually I won't use the editor no more

Why ?  

- Its just for setup the chip, set the allowed clks etc. ; so you need it always, if you want change something, 

then gen. code , -> you get your program with your new settings.

And having less than 50MHz for the ADC is not limiting, what you can do with the adc, except you go to its absolute speed limits, but that might be not the best idea, if you did nothing else until now, to get some experience with the ADC .

btw

I puzzled boost and Vos setting, but still there is some possible effect of the Vos setting: all max speeds depend on this, so maybe you cannot set every adc clock etc , if not on high Vos setting, for high clock speeds.

(But also more power consumption and higher chip temperature -> less live time . So just use as high, as needed.)