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STM32H755: flash write/erase issue with IWDG1/WWDG1 enabled

Associate II


We have a custom board based on STM32H755. We have two configuration of this SoC. In the normal operation we run a Bare-metal application on M7 and Zephyr OS application on M4 in a dual core mode. When requiring firmware update, we run a Zephyr application on M7 alone. 

1) In the dual core mode, M4 Zephyr OS sees two flash partitions

image2 - read only - 896KiB

bootloader - read/write - 128KiB

2) In the firmware update application

M7 sees both banks and following partitions

Bank 0

image1 - read-write- 896KiB

configuration read/write - 128KiB

Bank 1

image 2 - read-write- 896KiB

bootloader - read only - 128KiB

I am able to update bootloader partition in 1) without IWDG1/WWDG1 enabled. Similarly I am able to update image1,  configuration and image 2 partitions without IWDG1/WWDG1 enabled.

But when I enable IWDG1/WWDG1, firmware update doesn't work on Bank 1 partitions (bootloader partition in case 1) and image 2 partition on Bank 1. It either get hung or board reset reset cause Watchdog reset.

So there is some interaction between Flash erase/write on bank 1 with watchdog. Need your help to understand this issue and for a potential solution.


>If the M7 touches code in the erased bank it will hang too. Where is the code that resets the watchdog? 
For case 1) Bare-metal code on M7 does init and pet watchdog and is run from Bank0, where as erase/write done by Zephyr application on M4 and it runs from Bank 1