STM32H750 QUADSPI FIFO Question

[JCuna.1]

I read in the reference manual that the STM32H750 has a 32-byte fifo. FTHRES is the FIFO buffer and FLEVEL indicates how many values ​​are stored in the FIFO buffer. The reference manual also explains that after the FIFO is full the QSPI peripheral temporarily stops reading bytes (qspi_clk is suspended) to avoid an overflow and the byte reading process resumes after reading 4 bytes from the FIFO. But this shows FLEVEL <= 11 and I don't understand this because FIFO has a capacity of 32 bytes. So FLEVEL must be less than or equal to 28 bytes.

Also the reference manual explain that for FTHRES is greater or equal than 13, I need to read fifo in order to continue reading operation, and again this does not match with fifo size.

Am I missing something?

https://www.st.com/resource/en/reference_manual/dm00314099-stm32h742-stm32h743-753-and-stm32h750-value-line-advanced-arm-based-32-bit-mcus-stmicroelectronics.pdf