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STM32H743XI ADC DMA speed problem.

CChan.19
Associate II

I am using STM32H743XI to capture a image sensor signal by using ADC and DMA.

The image sensor signal is an analog signal following a 2.5MHz clock.

I planed to use ADC and DMA to capture an image frame in a memory buffer.

The size of the buffer is 268x180 half-words with only one image frame.

When I setup Timer8 in 2.5MHz in order to trigger the ADC sampling and DMA,

the result is a 4 images in one DMA image buffer.

It seems to be caused by slower ADC sampling rate.

After I reduce the 2.5MHz image signal clock to 1.25MHz,

there will be only one image in the DMA image buffer (ADC is still set in2.5MHz)​.

In the above case, I used 8-bit ADC resolution. If I used 16-bit or 14-bit,

the situation become worse. There will be more small images in one DMA buffer.

According to AN5354 (Getting started with the STM32H7 Series MCU 16-bit ADC) Application note, 

the max sampling rate in 14-bit is 3.1MHz at least.

I do not know how to reach this max speed of ADC. Is there any one can

give me a hint or example code? Any suggestion will be welcomed.

Thank you in advance.

Chih-Wei Chang​

7 REPLIES 7
MM..1
Chief

Thanks for your suggestion very much. But this example is using ADC and interrupt.

Do you suggest that ADC+Timer+interrupt is faster than ADC+DMA+Timer?

I thought DMA can improve the overall performance. Am I wrong?

Chih-Wei Chang​

I mean timer part and care for use only one edge for trigger. Too you dont write how you sync frame start usw.

For example if yu trig on both edges reult is 4 images

> (ADC is still set in2.5MHz)​.

What does that mean?

JW

I mean the Timer8 used to trigger ADC is in 2.5MHz.

The Timer8 is still keeping the same triggering frequency.

I only reduce the pixel frequency (frame rate) of the image sensor.

In AN Table 11 is all info.

ADC input multiplexer: The ADC has an input multiplexer that selects one of 20 channels to sample. There are 6 fast channels characterized with low input resistance. The other 14 channels have higher input resistances that require longer sampling times. These are hence referred to as slow channels. 

DMA cant limit this ADC .

For high ADC samplerate you need setup ADC clock high and conversion cycles low.

Tables 12-14 for your package is limiter.

The ADC+DMA will be started in the beginning of the image frame.

There is a signal to indicate the start of the image frame.

The ADC DMA will be restarted after the completion of the previous DMA

and in the beginning of the image frames.

I tried to trigger the ADC in both edges, but it does not make any difference.

4 images in one image buffer means the ADC DMA is slow, so that the second ADC DMA will start after 4 image frames were captured into the image frame buffer.​