2020-05-12 03:43 AM
After test we suspect it must be AXI Bus conflict cause to this bug. Maybe CPU and DMA are want to access same SDRAM at the same time. It never occur after we change DMA access address to SRAM2. It is severe bug.
I want to know it is a bug cause EN bit out of control or any other problem cause to it.
If any one have any idea, tell me please.
2020-05-12 09:32 AM
> EN bit can't be changed
Was there any DMA error status flash set for this stream before this happened?
Isn't there anything related in the errata?
JW
2020-05-12 11:47 PM
Unfortunately, We not found any error status when it happened. DMA_LISR and DMA_HISR seem ok.
2020-05-12 11:58 PM
Try asking ST directly through web support form.
JW