[STM32H7] When I set the MPU at the address 0x30000000,Program entry HardFault

[Passerby]

The configuration of Cubemx is as follows

The configured address is the address of SRAM1-3，given this configuration, why does "Strongly ordered memory" cause a HardFault

Thanks.

[Passerby]

Is it because the address of sram1-3 cannot be "Strongly ordered"?

Why?

[Sarra.S]

Hello @Passerby, welcome to ST Community, 

You can find below the MPU configuration for region0- this photo is from Managing memory protection unit in STM32 MCUs - Application note. 

 So in STM32CubeMX, the MPU shareability must be enabled for example, please refer to How to configure the MPU of an STM32 using STM32CubeMX.

[Passerby]

Hello,@Sarra.S

But it works when I set it to "TEX = 1   C = 0  B = 0  S = 0", shareability is disable，Why？

When I set it to  "TEX = 0   C = 0  B = 0  S = 1",it is cannot work。

Thanks.

[SofLit]

Hello,

Are you doing an Unaligned access to that memory region?

See: https://www.keil.com/support/docs/3777%20%20.htm

From ARM CM7 TRM:

[Passerby]

Hello @SofLit 

I use CubeMX ETH LWIP(LAN8742)  default settings ，does this result in unaligned access?The MPU is as I configured it.

I use cubemx 6.8.0 ,HAL FW_H7 v1.11.1

Thanks!

[SofLit · Accepted solution]

I don't know about LWIP, but you can check if you faced an unaligned access in your application by reading SCB_CFSR register:

If SCB_CFSR = 0x01000000 -> you have an unaligned access.

For your reference: https://developer.arm.com/documentation/dui0646/c/Cortex-M7-Peripherals/System-control-block/Configurable-Fault-Status-Register?lang=en#Cihgbdbi

[Passerby]

Hello@SofLit 

Thank you for your reply,I will try it tomorrow.It's already evening in our country,my board is not here with me.

Thanks!

[Passerby]

Hello @SofLit 

Thank you for your reply 。

I read the "SCB->CFSR" register, and when set to "device" or "strongy-ordered", it is indeed 0x0100 0000, which indicates an "Unaligned access UsageFault" error according to the register interpretation！

Thanks！