STM32H7 SPI - trying to increase Master SS Idleness (MSSI) - affects only first transaction

[Yoav Biderman]

Posted on May 24, 2018 at 13:11

Hi,

I'm using the NUCLEO-H743ZI board with the STM32H743 MCU.

I'm using the HAL SPI1 module to transmit a buffer of 4 words (16 bits) and receive the corresponding 4 words into another buffer.

The component the MCU is communicating with (an A2D component), requires a certain delay between the active SS edge and the clock toggle beginning. Reading the reference manual, I noticed the MSSI parameter that's supposed to control this. When I set the parameter for 15 SPI clock cycles, it does create a delay, but only before the first word transaction and not the following 3 (image attached - SPI clock in yellow, SS in green).

Did anyone encounter this?

Thanks,

Yoav

#stm32h7-spi

[Tesla DeLorean]

Sorry, bumping old zombie unanswered questions off my feed

[devinw]

I've come across this same issue too. The Master SS Idleness should affect every single transaction, not just the first. OR make a 2nd parameter that adds idle cycles between SS and clock. Right now the inter-data SS idleness parameter just changes the length of time the SS is high or low between transactions, but then it changes SS state and almost immediately pulses clock.

This is really important at high speeds because many SPI chips have a minimum setup time between SS edge and first clock cycle.

I had to downgrade my DAC's SPI speed from 50MHz to 25MHz to make sure the 5ns setup time was obeyed.

Also, another quirk is that when using hardware NSS, Cube MX (for me anyway (this is STM32H533RE)) sets the GPIO speed in the Init function to LOW no matter what the SPI speed is. It should scale with speed like the clock pin.