STM32H7 periodical TIM triggered SPI transfer w/o DMA?

[MSZB]

On a STM32H745ZI-Q - Board I want to create periodical 4-byte SPI transfers  triggered by a timer. 

So far I got this working the following way:

TIM triggers DMA
DMA initiates the SPI transfer.

However, the SPI transfer timing (CS low) has a high jitter of 100 ns, which is not acceptable.

To reduce the jitter: Is there any known way to trigger the SPI transfer start directly by a timer on this specific MCU (from reading the RM, I don't think so)? 

The data to be transfered could be written to the SPI FIFO in advance by an ISR triggered with a proper delay. 

[waclawek.jan]

> HSI is terrible concerning jitter, the clock on the Nucleo from ST-link is much better,

This Nucleo contains STLink V3, which by default outputs MCO generated from the same horrible-jittery HSI. It might be switchable to crystal-generated non-8-MHz, though.

JW

[MasterT]

Jitter is likely be a frquency beating, since SPI has it's own clock prescaler (MBR). Simple solution is to make SPI in "free run" mode - no issue with NSS pin driving, H7 has advenced SPI hardware, 

hspi2.Init.MasterInterDataIdleness = SPI_MASTER_INTERDATA_IDLENESS_02CYCLE;

Changing this parameter allows to make a "fine tunning" of the sampling rate. 

Than configure timers to run synchronously with SPI, divider steps to be about +- MBR divider values. Or route SCLK line to input capture of the timer and generate PWM back. 

[LCE]

Oh my, I forgot that the ST-link clock might come from its HSI...

@MSZB so this is really something you should check.
Unless you are sure that your initial clock source is not any HSI from anywhere, you really should check this.
And somewhere you can change the ST-link's MCO. Probably something ugly like 25 MHz / 3 = 8.333 MHz from its external crystal, but that will be much better than what comes from HSI.

[waclawek.jan]

@MasterT,

> Jitter is likely be a frquency beating, since SPI has it's own clock prescaler (MBR).

Do you know for fact that the baudrate clock generator is free-running?

I don't doubt it, I'm genuinely curious; this never occured to me as a possibility, but of course the SPI may've been designed in this way.

JW

[MasterT]

Yes, sure. SPI clock divider (MBR) is just same thing as prescaler in timers. So you can't run two timers in sync if one has prescaler set = 0 and another to something else. It would be possible only if first timer has ClockDivision1 = ClockDivision2 x Prescaler2

[MSZB]

HSE is used, 8 MHz MCO from ST-LINK. It's jitter is roughly 1 ns.

The jitter of the TIM12 output, which triggers the DMA, is ca. 40 ns (!). Maybe I'll have too look at the supply configuration in more detail. The board runs in Supply Config  3 (Internal SMPS and LDO cascaded).

Thats the clock configuration:

[LCE]

At least for some other H7s (H723, 725, 733, 735) the 960 MHz after DIVN1 would be too much.
Maybe you are above the limit and CubeMX doesn't recognize it?

[waclawek.jan]

> HSE is used, 8 MHz MCO from ST-LINK.

As I've said above, the primary clock there is *not* HSE but HSI.

> It's jitter is roughly 1 ns.

Cycle-to-cycle jitter of HSI may be way better than long-term jitter.

Try to switch STLink to output the HSE-originated 25MHz/3 clock, and change the target's clock accordingly.

JW

[MSZB]

> At least for some other H7s (H723, 725, 733, 735) the 960 MHz after DIVN1 would be too much.
> Maybe you are above the limit and CubeMX doesn't recognize it?

For H745 the limit is 960 MHz (from STM32H745xI/G, table 59)