STM32H7 periodical TIM triggered SPI transfer w/o DMA?

[MSZB]

On a STM32H745ZI-Q - Board I want to create periodical 4-byte SPI transfers  triggered by a timer. 

So far I got this working the following way:

TIM triggers DMA
DMA initiates the SPI transfer.

However, the SPI transfer timing (CS low) has a high jitter of 100 ns, which is not acceptable.

To reduce the jitter: Is there any known way to trigger the SPI transfer start directly by a timer on this specific MCU (from reading the RM, I don't think so)? 

The data to be transfered could be written to the SPI FIFO in advance by an ISR triggered with a proper delay. 

[MSZB]

Thanks for all the suggestions so far. Before trying these - back to the original question:
Is it possible to the trigger transfer start of the SPI peripheral directly by a timer TRGO, without having to generate the SPI timings (SCK and/or CS) by timers, and without using DMA, on the STM32H745ZI?

[Michal Dudka]

As far as i know, without DMA no.

[MSZB]

It's about the jitter from one SPI transmission to the next and in relation to a PWM signal. I.e. T and Td in the drawing below must be jitter free (< 5 ns) for all periods. 

 

[FBL]

Hello @MSZB 

Have you tried different clock prescaler, source ? Which VOS used? Please check Table 117 in DS for SPI dynamic characteristics as reference.

[Michal Dudka]

If jitter have to be under 5ns, then you have to generate all three signals by timers. Master timer should generate PWM and CS signal and (position adjustable) "TRGO" for slave timer. Slave timer should be "advanced one" (TIM1, TIM8) which have "repetition counter" and should run in One-shot mode. When master timer generate TRGO, then slave timer generate burst of SCK periods (defined by repetition counter value) and stops.This way you should be able to generate your pattern. SPI then should work independently as slave and feeded by DMA. 

[LCE]

DMA jitter might be caused by too much traffic on the busses. I had that problem when the CPU never slept and constantly checked some variables / peripherals much too often. As soon as I put the CPU to sleep most of the time, DMAs ran much "smoother". Maybe take a look at that when using DMA.

[TDK]

You're unlikely to achieve less than a couple ticks of delay jitter without DMA without extensive M7 core knowledge and optimization. Possible yes, practical no.

[MSZB]

Delay is no problem. Jitter is.

[TDK]

This is what I meant. It has been edited.

[LCE]

Just to make sure... what's your clock source?

HSI is terrible concerning jitter, the clock on the Nucleo from ST-link is much better, but surely not as good as a dedicated decent crystal or oscillator.