STM32H7 OctoSPI Multiplexing XIP

[WA]

I am designing a board with an STM32H725ZGT3. I would like to multiplex external Flash and RAM on the same Octospi bus and use the external flash as execute in place memory. Is this a supported configuration? 

[KDJEM.1]

Hello @WA and welcome to the community;

To enable the Multiplexed mode, at least one OCTOSPI I/O port signals and the CS signal from the other port must be accessible s explained in the below figure from AN5050

So, Multiplexed mode requires BOTH: OCTOSPIM_P2_NCS and OCTOSPIM_P1_NCS

as mentioned in the RM0468:

OCTOSPIn_NCS are not part of the multiplexing. Only OCTOSPIn_IOs, OCTOSPIn_DQS and OCTOSPIn_CLK / OCTOSPIn_NCLK are multiplexed.

When referring to the STM32H725 datasheet, you can find that the STM32H725ZGT6 supports the multiplexed mode. The OCTOSPIM_P1_NCS is available on PB6 and OCTOSPIM_P2_NCS is available on PG12 pins for STM32H725ZGT6. 

You can used the STM32CubeMX to enable the multiplexed mode.

The OCTOSPI supports the execution in place (XIP) thanks to its integrated prefetch buffer.

Thank you.

Kaouthar

[Tesla DeLorean]

Ok, but that's pin level multiplexing

The question was more about using two different memory types, the ability to use both, and further if concurrent Memory Mapped operation on one or both of the OCTOSPI1 and OCTOSPI2

If it is possible, please provide a worked example or demonstration..

It should be possible to use OCTOSPI1 at 0x90000000 and OCTOSPI2 at 0x70000000, map pins (less NCS) via OCTOSPIM, probably something I'd chose to prototype quickly first before committing to a PCB. In theory it looks like it might be achievable, at least at the hardware and bare-metal level. 

[KDJEM.1 · Accepted solution]

Hello;

An HyperFlash and HyperRAM memories with Multiplexed mode example is available in AN5050.

Thank you.

Kaouthar