Is there any information for the STM32H735-DK on how to configure the S70KL128 HyperRAM to work?
Unfortunately, there's no source code for the binary demo from ST, so I'm forced to try to get the HyperRAM working somehow.
And the forums only provide information about problems when trying to run it in memory-mapped mode.
So far, I haven't been able to read or write a single byte because:
- The access times, latency times, and the clock in the STM32H7 must be set correctly for the HyperRAM to be accessible at all.
- The settings in the HyperRAM itself also need to be configured (DDR/DTR, drive strength, latency, burst length).
When creating a new project with the default values in the STM32CubeIDE for the evaluation board, adjust the octospi clock to 100MHz (PLL2R) and attempting to read the hyperram with the debugger, the only output is:
Could not halt device (18)
Failed to read all registers from target
Target is not responding, retrying...
Target is not responding, retrying...
When importing parts from the STM32H7B3I evaluation board and setting the timing, I can actually read incorrect data without the debugger crashing.
Does anyone know what needs to be set for the generic parameters for the octospi2?
Generic
Fifo Threshold 1? or 4?
Device Size 32? 24? 128?
Chip Select High Time 1? 4?
Free Running Clock Disable? Enabled?
Clock Prescaler 1 (at 100MHz Clock ok)
Sample Shifting None ? Half Cycle?
Delay Hold Quarter Cycle Disable ? Enabled?
Chip Select Boundary 31 ? 0? 1? 20?
Delay Block Disable? Enabled?
Maximum Transfer 0 ? 64? 128000?
Refresh Rate 200 ? 64? 32?
HyperBus(TM)
RW Recovery Time 7? or 4? or 6?
Access Time 4? or 0?
Write Access Latency Enable ? Disable ?
Latency Mode Variable ? Fixed?
Has anyone a sourcecode snippet, to initialice the octospi2 (with working parameters like above) and to initialice the S70KL128 to get the hyperram working?
