2020-10-09 07:56 PM
Hi,everyone!
I want to know if FDCAN ( I'm using STM32H7) has lost the automatic Bus-off Recovery mechanism. Looking Forward to get your reply.
Thanks!
Solved! Go to Solution.
2024-03-05 01:09 AM
void CAN_bus_off_check_reset(FDCAN_HandleTypeDef *hfdcan) {
FDCAN_ProtocolStatusTypeDef protocolStatus = {};
HAL_FDCAN_GetProtocolStatus(hfdcan, &protocolStatus);
if (protocolStatus.BusOff) {
CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_INIT);
}
}
You can check when you send message to fifo or check it on bus-off call back:
when CAN init
HAL_FDCAN_ActivateNotification(&hfdcan2, FDCAN_IT_BUS_OFF, 0);
add call back func
void HAL_FDCAN_ErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t ErrorStatusITs) {
if (hfdcan == &hfdcan2) {
if ((ErrorStatusITs & FDCAN_IT_BUS_OFF) != RESET) {
CAN_bus_off_check_reset(hfdcan);
}
}
}
2020-10-14 02:59 AM
Hello @lshan.1 ,
Indeed, the FDCAN Peripheral is compliant with ISO 11898-1: 2015, regarding bus off recovery,
This note highlighted in the RM0433 -Rev7 (page 2557/3319):
“The Bus_Off recovery sequence (see CAN Specification Rev. 2.0 or ISO11898-1) cannot be shortened by setting or resetting FDCAN_CCCR.INIT. If the device goes Bus_Off, it will set FDCAN_CCCR.INIT of its own, stopping all bus activities. Once FDCAN_CCCR.INIT has been cleared by the CPU, the device will then wait for 129 occurrences of bus Idle (129 × 11 consecutive recessive bits) before resuming normal operation. At the end of the Bus_Off recovery sequence, the error management counters will be reset. During the waiting time after the reset of FDCAN_CCCR.INIT, each time a sequence of 11 recessive bits has been monitored, a Bit0 error code is written to FDCAN_PSR.LEC, enabling the CPU to readily check up whether the CAN bus is stuck at dominant or continuously disturbed and to monitor the Bus_Off recovery sequence. FDCAN_ECR.REC is used to count these sequences.�?
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Imen
2021-09-27 04:39 AM
Hi @Imen DAHMEN Thanks for your reply.
Is there any example on CubeMX software fro the STM32G4 series that describes this handling mechanism of BUS_OFF management?
2024-03-05 01:09 AM
void CAN_bus_off_check_reset(FDCAN_HandleTypeDef *hfdcan) {
FDCAN_ProtocolStatusTypeDef protocolStatus = {};
HAL_FDCAN_GetProtocolStatus(hfdcan, &protocolStatus);
if (protocolStatus.BusOff) {
CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_INIT);
}
}
You can check when you send message to fifo or check it on bus-off call back:
when CAN init
HAL_FDCAN_ActivateNotification(&hfdcan2, FDCAN_IT_BUS_OFF, 0);
add call back func
void HAL_FDCAN_ErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t ErrorStatusITs) {
if (hfdcan == &hfdcan2) {
if ((ErrorStatusITs & FDCAN_IT_BUS_OFF) != RESET) {
CAN_bus_off_check_reset(hfdcan);
}
}
}
2024-03-07 06:38 PM
Thank you very much for your reply. This solved my long-standing doubt. It turned out that I confused AutoRetransmission and BUS_OFF. Now I use STM32 H7 to automatically retransmit when BUS fails.