Hello,
I have been tasked recently with porting some code from another microcontroller into the STM32H7. Right now I am taking care of the UART communication and some parts around that. And I would like opinions and advice about some things if possible.
Since the architecture is quite a bit different and the clock is so high, I wanted to see how can I increase performance on previous implementations. Some targets will do quite a bit of math processing, while some will mostly communicate with multiple targets.
I've been looking at the documentation of the memories and DMA as well as AN4891.
Of note is that one target will be using ethernet.
Previous implementations of UART communication simply had a TX and RX interrupt sending/filling a buffer. Some had some DMA for TX.
My idea is to have:
CPU only using DTCM if possible for data.
CPU using ITCM for most (all?) ISRs.
CPU running code from flash with cache on.
This is to avoid cache misses which can happen (always?) during interrupts and to avoid wait-states and latency.
Then for UART communications (can be multiple UARTs) I would use DMA if needed/possible. The thing is, if I use code like the example "MDMA_GPDMA_Triggering" that would mean that the DTCM RAM would be frequently be accessed to store a few bytes and I am a bit worried about that. I was wondering if it was better to have a buffer in DTCM transfered into SRAM1 (maybe by MDMA), this would be really fast once, and then DMA would transfer to UART as the peripheral requested. And vice-versa for receiving data, the processor would request data from SRAM1 as needed to process.
If I needed big buffers that would not fit well in DTCM this might also help.
is this too far fetched?
