STM32G474 - HRTIM multi-phase pwm with pulse-pulse current limiting - not working.

[JCase.1]

Hi all -    I am building an isolated power converter using a three phase forward converter topology.  Each phase has a half bridge driving a transformer primary w.r.t. Vin/2 (split Vin).  The transformer has a mid-tap secondary, rectified effectively acting like a buck regulator at 2x the primary frequency.  I am using the HRTIM hardware to drive this.

So far it works great - I have my three phases A/B/C programmed like so (each has high-side 1, low-side 2):

A resets on master update, A1 set on A update, reset on A cmp1, A2 set on A cmp2, reset on A cmp3.

B resets on master cmp1, B1 set on master cmp1, reset on B cmp1, B2 set on B cmp2, reset on B cmp3.

C resets on master cmp2, C1 set on master cmp2, reset on C cmp1, C2 set on C cmp2, reset on C cmp3.

The master cmp1 and cmp2 are set at phase angles 60, 120.  The maset compares and all three cmp2 are fixed, while the cmp1 and cmp3 are all set by the feedback code.   Works perfectly.

For continuous mode, however, we can't run in voltage mode as there is no balancing of the phases, so we have to run in peak current mode.  I have CTs on each primary, rectified, feeding to comparator inputs on the CPU.  I have modified all the programming for the resets to reset EITHER on the above cmp1 or cmp3, or on an eevN mapped to the appropriate comparator output.   The -IN for each of the three comparators maps to DAC1 ch1.  I have set the DAC_MCR to 0x11 to connect only to internal peripherals, not external pin.  I have enabled the comparators with no blanking, no hysteresis, non-inv. 

I know the internal connections are working, because lowering the DAC value while running does cause early commutation, but it appears to latch on.  Raising the DAC value does not restore simple duty cycle control.  Also, it appears that using a single comparator on circuit A for reset of A1 and A2 seems to apply asymmetrically, as if it is latching on and not letting A2 fire.

Question 1:  Did I do something *** here, attempting to use a single rectified CT primary current signal to a single comparator for both A1 and A2 commutation?  I would think this is pretty standard.....

Question 2:  Is there some setting I am missing to unlatch/reset the reset sensitivity to the comparator?  I suspect that I am missing some subtlety in the EExFLTR settings regarding windowing and latching.  I am setting EEFxR1 latch bits in the sample code below, but have tried without with no apparent difference.

Question 3:  The eev1-eev5 appear to act differently than eev6-eev10.  The former allow for "fast" mode, while the latter allow for digital filtering.  Right now I am using the former, but now I see in fine print that when using external events for reset, it is edge sensitive even if set level sensitive, and fast mode not available....?  Should I be using eev6-10 with digital filtering?

Below is my init code for the HRTIM.  (All hard coded in gnu assy, not using Cube).  (write is a simple macro using R0 & R1, self-explanatory.   pause is a routine using TIM6 for various housekeeping delays.)  For now I am focusing on channel A only -- I have good gate pulses for all six FETs, but right now I have FETs and transformer populated only for channel A to verify function of Ipk limiting.

Any help is appreciated.      - Jeff Casey

	write	HRTIM_DLLCR,1		// start the calibration by setting CAL bit
	write	TIM6_ARR,99999
	bl	pause			// wait 100 ms for DLL to stabilize
	write	HRTIM_DLLCR,1<<1	// set CALEN on for regular re-calibrations

	write	HRTIM_MCR, 0x2800000A	// MREPU on, PREEN on, timers not yet enabled, no sync, CONT on, CKPSC=010 (*8)
	write	HRTIM_MCNTR,0		// master counter

	write	HRTIM_TIMACR,0x0802000A	// PREEN on, CKPSC=010, continuous, TxREPU
	write	HRTIM_TIMBCR,0x0802000A	// same
	write	HRTIM_TIMCCR,0x0802000A	// same

	write	HRTIM_CNTAR,0  
	write	HRTIM_CNTBR,0  
	write	HRTIM_CNTCR,0

	write	HRTIM_MPER,  37499  // ARR sets main period.  1.2 GHz/32 kHz t=0 phA, on A1
	write	HRTIM_MCMP1R, 6249  // phase=60 deg	 t=0 phB, on B1
	write	HRTIM_MCMP2R,12499  // phase=120 deg	 t=0 phC, on C1

	write	HRTIM_CMP1AR,7000  // feedback adjust from 30-18720  reset phA, off A1
	write	HRTIM_CMP1BR,7000  // same			     reset phB, off B1
	write	HRTIM_CMP1CR,7000  // same			     reset phC, off C1

	write	HRTIM_CMP2AR,18749  // 50% point, fixed		     on A2
	write	HRTIM_CMP2BR,18749  // same			     on B2
	write	HRTIM_CMP2CR,18749  // same			     on C2

	write	HRTIM_CMP3AR,25750  // feedback adjust from (30-18720)+18750	off A2
	write	HRTIM_CMP3BR,25750  // same					off B2
	write	HRTIM_CMP3CR,25750  // same					off C2

	write	HRTIM_RSTAR, 1<<4   // A resets on MSTPER (Master timer period)
	write	HRTIM_SETA1R,1<<31  // bit 31 = A1 set on A update
	write	HRTIM_RSTA1R,0x01000008 // bit3=A1 rst on A cmp1, bit24 rst eev4=COMP1.out
	write	HRTIM_SETA2R,1<<4   // bit 4  = A2 set on A cmp2
	write	HRTIM_RSTA2R,0x01000020 // bit5=A2 rst on A cmp3, bit24 rst eev4=COMP1 out
	write	HRTIM_EEFAR1,1<<18	// latch bit for eev4

	write	HRTIM_RSTBR, 1<<5   // B resets on MSTCMP1 (Master timer compare 1)
	write	HRTIM_SETB1R,1<<8   // bit 8  = B1 set on M cmp1
	write	HRTIM_RSTB1R,0x02000008	// bit3=B1 rst on B cmp1, bit25 rst eev5=COMP3 out
	write	HRTIM_SETB2R,1<<4	// bit 4  = B2 set on B cmp2
	write	HRTIM_RSTB2R,0x02000020	// bit5=B2 rst on B cmp3, bit25 rst eev5=COMP3 out
	write	HRTIM_EEFBR1,1<<24	// latch bit for eev5

	write	HRTIM_RSTCR, 1<<6	// C resets on MSTCMP2 (Master timer compare 2)
	write	HRTIM_SETC1R,1<<9	// bit 9  = C1 set on M cmp2
	write	HRTIM_RSTC1R,0x00400008	// bit3=C1 rst on C cmp1, bit22 rst eev2=COMP4.out
	write	HRTIM_SETC2R,1<<4	// bit 4  = C2 set on C cmp2
	write	HRTIM_RSTC2R,0x00400020	// bit5=C2 rst on C cmp3, bit 22 rst eev2=COMP4.out
	write	HRTIM_EEFCR1,1<<6	// latch bit for eev2

	write	HRTIM_EECR1,0x29A40A40	// map comparators to HRTIM, fast, edge triggered

	write	HRTIM_OUTAR,0x00200020	// fault=inact, idle=inact, pol-acthi, both A1 & A2
	write	HRTIM_OUTBR,0x00200020	// same
	write	HRTIM_OUTBR,0x00200020	// same