1 ACCEPTED SOLUTION
Accepted Solutions
I've still haven't found a solution to the HRTIM ADC Trigger, but I've managed a workaround in calling the LL_ADC_REG_StartConversion inside TIMER B HRTIM_TIMB_IRQn_IRQHandler.
TIMER B is a dedicated UP-COUNTING timer, with CMP1 configured at 50% DutyCycle.
The workaround is functional, but not optimal, even if the TIMER B is "statically configured" the IRQ does not latch with a constant period, sometime pulses are skipped (TIMER B CMP1 is the only and highest IRQ).
Here follows the TIMER B init code:
// > HRTIM Channel B Configuration Block (ADC SW Trigger)
// Time Base Settings:
LL_HRTIM_TIM_SetPrescaler(HRTIM1, LL_HRTIM_TIMER_B, LL_HRTIM_PRESCALERRATIO_MUL8);
LL_HRTIM_TIM_SetPeriod(HRTIM1, LL_HRTIM_TIMER_B, iInverter_PWM_Level);
LL_HRTIM_TIM_SetRepetition(HRTIM1, LL_HRTIM_TIMER_B, 0x00);
// Time Base Settings:
// The Timer is set in Up-Down Center-Aligned Mode. It's event generation IP is
// configured in "crest" mode (events are generated when counter reach period value).
// By now only the master timer PER event is used, slave event are just configured.
LL_HRTIM_TIM_SetCountingMode(HRTIM1, LL_HRTIM_TIMER_B, LL_HRTIM_COUNTING_MODE_UP);
LL_HRTIM_TIM_SetRollOverMode(HRTIM1, LL_HRTIM_TIMER_B, LL_HRTIM_ROLLOVER_MODE_PER);
LL_HRTIM_TIM_SetFaultEventRollOverMode(HRTIM1, LL_HRTIM_TIMER_B, LL_HRTIM_ROLLOVER_MODE_PER);
LL_HRTIM_TIM_SetBMRollOverMode(HRTIM1, LL_HRTIM_TIMER_B, LL_HRTIM_ROLLOVER_MODE_PER);
LL_HRTIM_TIM_SetADCRollOverMode(HRTIM1, LL_HRTIM_TIMER_B, LL_HRTIM_ROLLOVER_MODE_PER);
LL_HRTIM_TIM_SetOutputRollOverMode(HRTIM1, LL_HRTIM_TIMER_B, LL_HRTIM_ROLLOVER_MODE_PER);
// Time Base Settings:
// Counter in Free-Run (Continuous Mode)
LL_HRTIM_TIM_SetCounterMode(HRTIM1, LL_HRTIM_TIMER_B, LL_HRTIM_MODE_CONTINUOUS);
// Timing Unit:
LL_HRTIM_TIM_SetInterleavedMode(HRTIM1, LL_HRTIM_TIMER_B, LL_HRTIM_INTERLEAVED_MODE_DISABLED);
LL_HRTIM_TIM_DisableHalfMode(HRTIM1, LL_HRTIM_TIMER_B);
LL_HRTIM_TIM_DisableStartOnSync(HRTIM1, LL_HRTIM_TIMER_B);
LL_HRTIM_TIM_DisableResetOnSync(HRTIM1, LL_HRTIM_TIMER_B);
LL_HRTIM_TIM_SetDACTrig(HRTIM1, LL_HRTIM_TIMER_B, LL_HRTIM_DACTRIG_NONE);
LL_HRTIM_TIM_DisablePreload(HRTIM1, LL_HRTIM_TIMER_B); // Must be disabled as CNT1 is used.
LL_HRTIM_TIM_SetUpdateGating(HRTIM1, LL_HRTIM_TIMER_B, LL_HRTIM_UPDATEGATING_INDEPENDENT);
LL_HRTIM_TIM_SetBurstModeOption(HRTIM1, LL_HRTIM_TIMER_B, LL_HRTIM_BURSTMODE_MAINTAINCLOCK);
LL_HRTIM_TIM_DisablePushPullMode(HRTIM1, LL_HRTIM_TIMER_B);
LL_HRTIM_TIM_SetUpdateTrig(HRTIM1, LL_HRTIM_TIMER_B, u32_HRTIM_UpdateTrig);
LL_HRTIM_TIM_DisableResyncUpdate(HRTIM1, LL_HRTIM_TIMER_B);
LL_HRTIM_TIM_SetResetTrig(HRTIM1, LL_HRTIM_TIMER_B, u32_HRTIM_ResetTrig);
// Compare Unit 1:
// Duty is set to 50% FIXED, as this is for ADC Trigger Generation
LL_HRTIM_TIM_SetComp1Mode(HRTIM1, LL_HRTIM_TIMER_B, u32_HRTIM_SetComp1Mode);
LL_HRTIM_TIM_SetCompare1(HRTIM1, LL_HRTIM_TIMER_B, (iInverter_PWM_Level>>1));
// Wait for configuration applied
while(LL_HRTIM_IsActiveFlag_DLLRDY(HRTIM1) == RESET){};
// Enable TIMERB CMP1 interrupt */
LL_HRTIM_EnableIT_CMP1(HRTIM1, LL_HRTIM_TIMER_B );
NVIC_EnableIRQ( HRTIM1_TIMB_IRQn );
NVIC_SetPriority( HRTIM1_TIMB_IRQn, 0 );The ISR code to manage TIMERB CMP1, toggle of a pin (simulating ADC Triggering):
void HRTIM_TIMB_IRQn_IRQHandler (void) { //HRTIM_Master_IRQn_IRQHandler( void ){
// Code must check for a specific enabled flag
if( LL_HRTIM_IsActiveFlag_CMP1( HRTIM1, LL_HRTIM_TIMER_B ) == 1 ){
LL_HRTIM_ClearFlag_CMP1( HRTIM1, LL_HRTIM_TIMER_B );
vGpioAPI_Toggle(xGpioAPI_XMI_GPIO2);
}
}Here follows the scope acquisitions of the issue, highlighted in red:
- in yellow is the CENTER ALIGNED PWM output of TIMER A, with a varying duty cycle
- in blue the vGpioAPI_Toggle(xGpioAPI_XMI_GPIO2) function, called inside the TIMERB CMP1 IRQ, with fixed 50% duty.
Dear @Francois VILMAIN ,
Thank you for your answer.
I've tried to replicate the configuration you've suggested but I still get an erroneous behaviour of the HRTIM peripheral.
That's my minima init of HRTIM, that results in the same Common & Master register configuration as indicated in your register snapshot.
HRTIM1->sMasterRegs.MCR |= 0x2001000B;
HRTIM1->sMasterRegs.MDIER |= 0x00000010;
HRTIM1->sMasterRegs.MCNTR = 0x00000000;
HRTIM1->sMasterRegs.MPER = 2*iInverter_PWM_Level;
HRTIM1->sMasterRegs.MCMP1R = iInverter_PWM_Level;
// a) CMP1 Tentative
LL_HRTIM_ConfigADCTrig(HRTIM1, LL_HRTIM_ADCTRIG_1, LL_HRTIM_ADCTRIG_UPDATE_MASTER, LL_HRTIM_ADCTRIG_SRC13_MCMP1);
// b) MPER Tentative
//LL_HRTIM_ConfigADCTrig(HRTIM1, LL_HRTIM_ADCTRIG_1, LL_HRTIM_ADCTRIG_UPDATE_MASTER, LL_HRTIM_ADCTRIG_SRC13_MPER);
// Postascaler
LL_HRTIM_SetADCPostScaler(HRTIM1, LL_HRTIM_ADCTRIG_1, 20);On the ADC Side, EXTSE bits have the right pattern [10101], EXTEN have rising edge [01].
That is done by the following instructions:
// Enable the ADC external trigger
LL_ADC_REG_SetTriggerSource( ADC1, LL_ADC_REG_TRIG_EXT_HRTIM_TRG1 );
LL_ADC_REG_SetTriggerEdge(ADC1, LL_ADC_REG_TRIG_EXT_RISING);If, instead of External, I configure the ADC to use the Software Trigger with "LL_ADC_REG_SetTriggerSource( ADC1, LL_ADC_REG_TRIG_SOFTWARE )", the acquisition pattern starts and complete without issue.
I believe my problem is that the HRTIM is not generating the TRG1 but I really cannot understand the reason. Attached you can find my registers snapshot: maybe you can spot the elephant in the room.
Thank you,
Davide
