STM32G4 Timer Break On Exceptions

[JVinc.1]

Hello,

I would like to test the behaviour of STM32G4 MCU timers on exceptions. The SYSCFG register has several options for timer break. The HAL library provides the following macros to activate these options:

__HAL_SYSCFG_BREAK_ECC_LOCK();

__HAL_SYSCFG_BREAK_PVD_LOCK();

__HAL_SYSCFG_BREAK_SRAMPARITY_LOCK();

__HAL_SYSCFG_BREAK_LOCKUP_LOCK();

How can I generate exceptions for each case: FLASH ECC error, PVD error, SRAM Parity error, Core Lockup? Are there any example software test routines to generate them?

[JVinc.1]

Is there any update?

[waclawek.jan]

PVD is probably the easiest: set up the PVD level in PWR_CR2.PLS and enable it in PWR_CR2.PVDE, then decrease voltage below the set level. It's not clear from the description, whether EXTI for EXTI16 has to be set somehow for the timers' break to function; I'd say no, but it's easy to try.

SRAM should be relatively easy, too - reading from SRAM with enabled ECC without prior writing to it will quite likely throw the error. If not one address, simply try more.

FLASH is not easy and has been discussed e.g. here: https://community.st.com/s/question/0D50X00009XkWlVSAV/stm32l476-how-can-i-create-an-ecc-error-to-test-my-error-handling

I'm not sure about the Core Lockup; read ARMs documents: Cortex-M4 TRM and the ARMv7M ARM.

JW