STM32G4 CAN TX buffer

[Moritz1]

Hello,

I'am currently programming on a STM32G473. I'am sending CAN Message via the FDCAN peripheral.
In generally everything works, all my messages I put into the Tx Buffer are sent.

But in one little detail I'am confused:

In Figure 669 its described, that the TX buffer consists of 3 elements.

But if I want to find out in which index I have to put the next message by reading the TXFQS_TFQPI field, I'am confused why the reference manual describes a range of 0-3 for this field. So it seems that there are 4 messages? But in the Add-Request Register (TXBAR_AR) there are only 3 Bits for adding transmission requests (and the RAM buffer has only space for 3 Messages).

• If the put index is 0 --> I set the Bit 0 in TXBAR_AR
• If the put index is 1 --> I set the Bit 1 in TXBAR_AR
• If the put index is 2 --> I set the Bit 2 in TXBAR_AR
• If the put index is 3 --> What should I do? There is no bit for a fourth request (and also no space in Buffer for a fourth message)

So is it maybe an error in the reference manual and the range of TXFQS_TFQPI is only 0-2 and in reality the peripheral will never give me a 3 in this field?

Or, if the range 0-3 is correct: What should I do if I get a put-Index of 3?

[Ref: RM0440, Rev. 8]

[MHoll.2]

Good catch!

I think You are right this is a error in the Reference manual.

At least the HAL driver uses the TFQPI field with out any check for values > 2 (this would write the Message outside of the Message RAM!).

Let's see if some one from ST has some insight.

Martin

[Oleksii]

Perhaps 3 means the buffer is full.
And there is nowhere else to write))

[MHoll.2]

If this were the case then the HAL driver would lose TX messages (writing outside the Buffer memory and enabling a not present TXBAR AR Bit!)

[Moritz1]

@Oleksii: I dont think so. There is a dedicated Bit TXFQS_TFQF which is the "Tx FIFO/Queue full" indication.

[Oleksii]

Have you ever thought about the fact that 3 (0b11),
is a trigger for the bit TXFQS_TFQF = 1))

[Oleksii]

HAL_StatusTypeDef HAL_FDCAN_AddMessageToTxFifoQ(FDCAN_HandleTypeDef *hfdcan, const FDCAN_TxHeaderTypeDef *pTxHeader,
                                                const uint8_t *pTxData)
{
  uint32_t PutIndex;

  /* Check function parameters */
  assert_param(IS_FDCAN_ID_TYPE(pTxHeader->IdType));
  if (pTxHeader->IdType == FDCAN_STANDARD_ID)
  {
    assert_param(IS_FDCAN_MAX_VALUE(pTxHeader->Identifier, 0x7FFU));
  }
  else /* pTxHeader->IdType == FDCAN_EXTENDED_ID */
  {
    assert_param(IS_FDCAN_MAX_VALUE(pTxHeader->Identifier, 0x1FFFFFFFU));
  }
  assert_param(IS_FDCAN_FRAME_TYPE(pTxHeader->TxFrameType));
  assert_param(IS_FDCAN_DLC(pTxHeader->DataLength));
  assert_param(IS_FDCAN_ESI(pTxHeader->ErrorStateIndicator));
  assert_param(IS_FDCAN_BRS(pTxHeader->BitRateSwitch));
  assert_param(IS_FDCAN_FDF(pTxHeader->FDFormat));
  assert_param(IS_FDCAN_EFC(pTxHeader->TxEventFifoControl));
  assert_param(IS_FDCAN_MAX_VALUE(pTxHeader->MessageMarker, 0xFFU));

  if (hfdcan->State == HAL_FDCAN_STATE_BUSY)
  {
    /* Check that the Tx FIFO/Queue is not full */
    if ((hfdcan->Instance->TXFQS & FDCAN_TXFQS_TFQF) != 0U)
    {
      /* Update error code */
      hfdcan->ErrorCode |= HAL_FDCAN_ERROR_FIFO_FULL;

      return HAL_ERROR;
    }
    else
    {
      /* Retrieve the Tx FIFO PutIndex */
      PutIndex = ((hfdcan->Instance->TXFQS & FDCAN_TXFQS_TFQPI) >> FDCAN_TXFQS_TFQPI_Pos);

      /* Add the message to the Tx FIFO/Queue */
      FDCAN_CopyMessageToRAM(hfdcan, pTxHeader, pTxData, PutIndex);

      /* Activate the corresponding transmission request */
      hfdcan->Instance->TXBAR = ((uint32_t)1 << PutIndex);

      /* Store the Latest Tx FIFO/Queue Request Buffer Index */
      hfdcan->LatestTxFifoQRequest = ((uint32_t)1 << PutIndex);
    }

    /* Return function status */
    return HAL_OK;
  }
  else
  {
    /* Update error code */
    hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_STARTED;

    return HAL_ERROR;
  }
}

Automatic platoon TXFQS_TFQF = 1,
Does not lead to message loss.