STM32G0B1 programming Option Bytes stopped after OBL_Launch
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‎2021-11-04 6:55 AM
The MCU stops when the program reaches this line (FLASH->CR |= FLASH_CR_OBL_LAUNCH;) in the function below.
The option bytes I want to write are at the moment still unchanged to the delivery state. Later they will be changed to RDP Level 1.
void Optionbytes_Config(void)
{
Flash_Unlock();
Optionbytes_Unlock();
FLASH->OPTR = 0xFFFFFEAA;
while((FLASH ->SR & FLASH_SR_BSY1) == FLASH_SR_BSY1);
FLASH->CR |= FLASH_CR_OPTSTRT;
while((FLASH ->SR & FLASH_SR_BSY1) == FLASH_SR_BSY1);
FLASH->CR &= ~FLASH_CR_OPTSTRT;
FLASH->CR |= FLASH_CR_OBL_LAUNCH;
while((FLASH ->SR & FLASH_SR_BSY1) == FLASH_SR_BSY1);
FLASH->CR |= FLASH_CR_LOCK;
FLASH->CR |= FLASH_CR_OPTLOCK;
}
Thank you for your help.
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‎2021-11-11 6:32 AM
I made it. My workaround is that I now set the optionbytes directly at the end of the hex file.
Only the two marked lines need to be inserted.
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‎2021-11-04 10:08 AM
See RM0444, 5.1.2: "Option byte loader reset
The option byte loader reset is generated when the OBL_LAUNCH bit (bit 27) is set in the
FLASH_CR register. This bit is used to launch the option byte loading by software."
BTW: "FLASH->CR &= ~FLASH_CR_OPTSTRT;" does nothing, OPSTSRT is reset automatically.
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‎2021-11-05 4:29 AM
Thank you for your reply.
I have removed this line, but it does not change anything.
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‎2021-11-05 5:05 AM
The point is, setting OBL_LAUNCH causes a RESET.
Of course, removing this line won't change anything.
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‎2021-11-11 6:32 AM
I made it. My workaround is that I now set the optionbytes directly at the end of the hex file.
Only the two marked lines need to be inserted.
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‎2021-12-09 4:38 AM
I experienced a similar issue with an STM32F030, which just "hangs" after setting FLASH_CR_OBL_LAUNCH bit in FLASH->CR register.
According to the reference manual (RM0360, 3.5.5, page 61) the STM32F030 should reset after setting FLASH_CR_OBL_LAUNCH, but it just "hangs" and stops executing any further instruction. (A following power cycle will set the option bytes though.)
My workaround is the usage of the independent watchdog (IWDG) which generates a system reset after setting FLASH_CR_OBL_LAUNCH in FLASH->CR register, which luckily also sets the option bytes as expected.
There's another solution shown in this thread, using standby mode and RTC wakeup from standby.
The whole thing might be an undocumented errata (at least of the STM32F0 series)(?)
Just my 2 cents.
