2025-06-12 2:19 AM - last edited on 2025-06-12 2:31 AM by mƎALLEm
Hello ST Team,
We are currently working with the STM32G0B1KCUX series MCU, which has 144 KB RAM and 256 KB Flash.
Our objective is to measure the frequency of an incoming signal using TIM1 in Input Capture mode with DMA (Channel 2). Below are the key configuration and issue details:
We are interested in capturing frequency using DMA mode without any interrupt callbacks. We need a way to synchronize the transfer completion to ensure the captured data is correct
i have Attached timer settings and code snippet
Timer Configuration:
Timer: TIM1 (16-bit)
Clock Frequency: 64 MHz (no prescaler)
DMA: Used to capture values without interrupt
Slave Mode: Reset mode with trigger on TI1FP1
Input Signal:
Frequency Range: 15.8 kHz to 16 kHz
Signal Period: Approximately 62.5 µs to 63.3 µs
Observation:
When checking the DMA_ISR_TCIF2 flag before reading, the time between frequency measurements varies inconsistently — sometimes 1ms, 2ms, or 3ms.
However, if we remove the DMA complete flag check, the capture reads occur at a rate matching the system clock and signal input, i.e., much faster and more consistent.
We are confused why adding this DMA transfer complete flag check:
results in millisecond-level delays between readings, even though the input signal is at ~63 µs intervals. Without this check, data comes in faster, matching expectations.
2025-06-12 2:49 AM - edited 2025-06-12 2:50 AM
It appears that you've set up the slave-mode controller in Reset mode triggered from channel 1, i.e. the setup which is in RM called "PWM Input". That alone should be enough to measure frequency, you shouldn't need DMA for that. At the same time, in that setup, it's unlikely two successive readings would result in any significant difference - regardless of whether in us or ms - if the input signal's frequency is stable.
So, either you don't show us relevant portions of the setup and relevant portions of code, or the input signal is intermittent.
Also, note, that it's not unlikely that Cube/HAL interrupt handlers would execute for hundreds to thousands of cycles, i.e. up to tens of us.
JW
2025-06-12 3:21 AM
2025-06-12 6:19 AM
> We are confused why adding this DMA transfer complete flag check:
> results in millisecond-level delays between readings,
Because the flag is checked and cleared within the HAL_DMA_IRQHandler. You should leave it alone, or you should remove the call to HAL_DMA_IRQHandler if you want to handle it yourself and implement your own handling of the flag.