STM32F429i-DISCO with 512Mbx16b memory

[megahercas6]

Posted on February 06, 2017 at 12:34

Hello, in my project i need to have more SDRAM than original 4M*16b.

So i ordered 32M x 16b ISSI IS42S16320d-7TL that fit's inside the same footprint, and i soldered single jumper cable to PG2 as well as modified GPIO init code for this pin.

But what else do i need to modify in order to run this memory ?

In examples i runned SDRAM test code that checks all SDRAM but even

  FMC_SDRAMInitStructure.FMC_ColumnBitsNumber = FMC_ColumnBits_Number_10b; ( changed from 8b to 10b)  /* Column addressing: [11:0] */  FMC_SDRAMInitStructure.FMC_RowBitsNumber = FMC_RowBits_Number_13b;//FMC_RowBits_Number_12b; (this is also changed to 13b from 12b)

Is that it, or should i do more ?  ( problem is that shorting PG2 to ground, example did not generate any problem)

[megahercas6]

Posted on February 08, 2017 at 10:16

No one ?

[waclawek.jan]

Posted on February 08, 2017 at 10:49

What is exactly the problem, again?

[megahercas6]

Posted on February 08, 2017 at 19:16

Is that sometimes memory check works, second time it does not, show error ( one byte from 512Mb is wrong), and so on. Random fault, even if all of the parameters of SDRAM are the same. So i just don't know where is the problem ? Clock is stock 180MHz

Or that all of the pins go to headers, that have negative impact on signal integrity ?

[waclawek.jan]

Posted on February 08, 2017 at 21:45

Or that all of the pins go to headers, that have negative impact on signal integrity ?

Surely the lines' length and shape has an impact, but it used to work with the original memory. You did not attach anything to SDRAM's lines, did you?

The PG2 line - the one which has been added - is now relatively long compared to others. Can that problem be identifiable as PG2/A12-specific? Could you cut the line from mcu to header and jumper it directly from the mcu to the memory?

JW

[T J]

Posted on February 09, 2017 at 00:07

I would say that you may have half or quarter the capacity that you think you have.

Write the 16bit Block number into each 8K boundary, then read the block 0 number, it will read the last mirrored block number.

if you are correct and you have the occasional error, maybe the CAS and RAS refresh system is not working hard enough, this will give you odd memory address verification failures.

what are your CAS and RAS latency values ?  (CAS can only be 2 or 3 clocks for this SDRAM)

Row and Column addressing 10b,13b is correct.

the speed grade of -7 memory chip has maximum 143MHz bus clock., what external clocking rate are you running ?

I have successfully installed a 8Mx16 on my STM32F746 PCB, but it was a -6 chip... good for 166MHz

what was the speed of the chip you removed ?