STM32F407 Uart DMA transfer overrun condition

[francescatodiego]

I need some clarification on using the Uart device in DMA mode

how should i handle the overrun condition (ORE bit set in SR register) ?

The read sequence SR and DR register reset the ORE bit

In DMA mode how I can do this ?

I must enable the EIE bit in CR3 register and do the reading sequence in the dma_rx_stream interrupt handler ?

static __irq void uB_UART6_DMA_RX_STREAM_handler()
{
//  uint32_t Intstatus = USART6->SR  ;
//  uint32_t data      = USART_ReceiveData(USART6) ;
 
  uint32_t dma_isr_flags = uB_DMA_Stream_IsrFlagStatus (Uart[UART6_PORT].rx_stream) ;
 
  uB_DMA_Stream_IsrFlagClear (Uart[UART6_PORT].rx_stream, dma_isr_flags);
 
  if (dma_isr_flags & (DMA_ITF_TE | DMA_ITF_DME))
  {
    DMA_Cmd     (Uart[UART6_PORT].rx_stream, DISABLE);
    USART_DMACmd(USART6, USART_DMAReq_Rx,    DISABLE);
 
    if (Uart[UART6_PORT].rxcb) Uart[UART6_PORT].rxcb(UART_RX_ERROR, 0, 0) ;
 
    Uart[UART6_PORT].rxget = 0 ;
 
    DMA_Cmd      (Uart[UART6_PORT].rx_stream, ENABLE);
    USART_DMACmd (USART6, USART_DMAReq_Rx,    ENABLE);
  }
}

Or the DMA transfer handles overrun clear the ORE bit and set the DMA transfer error bits in the appropriate LISR/HISR register ?

Thanks

[TDK]

Clearing ORE in DMA mode is the same as in non-DMA mode.

However, if ORE got set, it means your DMA did not handle the request. ORE is an error flag and should not be set during normal communication. You're missing data. I would look at why it's getting set and fix that.

[waclawek.jan]

> I must enable the EIE bit in CR3 register and do the reading sequence in the dma_rx_stream interrupt handler ?

Yes, but I don't understand your code, apparently you are using some unusual "library".

> Or the DMA transfer handles overrun clear the ORE bit and set the DMA transfer error bits in the appropriate LISR/HISR register ?

No. DMA is not aware of anything what happens in UART, except RXNE and TXE (in respective DMA Streams, if respective enable bits in UART are set and appropriate Channel in DMA Stream is selected).

JW

[francescatodiego]

Thanks for replies

The overrun isn't a real problem but I ask how to handle it if arise I am agree TDK normally the ORE flag never can be set in DMA transfer but we want prevent....

Library is an own older Library write around SPL (I think this is the name of library before ST HAL/LL) we have on plan to upgrade it to LL from few years... but the library is tested with various applications and the upgrade requires a lot of work and test

[waclawek.jan]

> Library is an own older Library

I understand; it's just that if you post code based on your own library, it has no meaning for us as we don't know what's in that library. There's no point for us to guess just based on functions/variables names, they may be misleading.

So, reiterating:

>> I must enable the EIE bit in CR3 register and do the reading sequence in the dma_rx_stream interrupt handler ?

Yes, but the reading sequence is to be  done in the USART interrupt handler, EIE is an USART interrupt, DMA does not know about USART features.

 

JW

[francescatodiego]

Ok for the code I am sorry, my question could have been more general without adding my code

Your reply confuse me a bit.

ORE can't generate itself an interrupt but is associtate to receive flag RXNE that generate Uart interrupt. Or rather the Uart interrupt must check the status of the error bits when receive a byte

The Uart RX interrupt (RXNE flag) will be generated also if configured in DMA mode ?

In the figure you posted there is a comment say the DMA clear the RXNE bit. And this is resonable DMA read the Uart DR register and the read access at Uart DR register reset the RXNE to zero

___________________________

Sorry after write my reply I read one more time your previous reply and I think I understand

EIE flag !!! enable Uart interrupt where I can check the Uart error bits ...

Now is clear

Thanks