STM32F4 - Master Receive

[dibs]

Posted on December 04, 2013 at 22:45

I am attempting to get an STM32F4 to receive data in Master mode. I am getting a problem where the RXNE interrupt is never tripped.

*Should this work, even if you have MISO tied to GND or 3.3V?*Do I need to do anything with the NSS in the peripheral?**Ignore the CS requirements of the slave for now. #stm32f4 #spi

[Tesla DeLorean]

Posted on December 04, 2013 at 23:07

There should be some master/slave examples in the firmware library.

You will however need to send some data to generate clocks for the slave to send data back to you. Reading SPIx->DR just reads an internal register, it does not generate any clocks.

[dibs]

Posted on December 04, 2013 at 23:13

If I write to the SPIx->DR, under what conditions will I get the RXNE register to be set? Let's say, I don't have a slave connected, but tie MISO to 3.3V. Should the MCU still tell me that I have received data?

[dibs]

Posted on December 04, 2013 at 23:14

If I write to the SPIx->DR, under what conditions will I get the RXNE register to be set? Let's say, I don't have a slave connected, but tie MISO to 3.3V. Should the MCU still tell me that I have received data?

[Tesla DeLorean]

Posted on December 04, 2013 at 23:30

The clocking in of the data occurs at the master, you should be able to control the edge/phase of the clock which MISO is sampled, but you are generating the clock, and the state of the data is of little consequence.

You should clear RXNE by reading SPIx->DR, when you send data by writing SPIx->DR, TXE should assert as the first bit leaves the master, RXNE should assert after the last bit leaves the master, and the last slave bit is clocked back.

[dibs]

Posted on December 05, 2013 at 15:06

Am I correct in saying that, from the Master's perspective, none of this is dependent on the CS or any NSS register?

[francescatodiego]

Posted on December 05, 2013 at 22:13

As

Clive

says,

there are plenty of

http://eliaselectronics.com/stm32f4-tutorials/stm32f4-spi-tutorial/

Surely

you've already done

but

checking

the check list

1- Enable clock for SPI and GPIO 2- Configure GPIO for alternate Function 3- Init the SPI (with std.library Spi_Init(Spibase, cfg) (cfg is the SPI config structure) 4- Init NVIC and define SPI isr handler(not mandatory) 5-Enable SPI (with std.library SPI_Cmd(Spibase, ENABLE)

It is not

necessary to configure

NSS

or

CS

(obviously

for

a simple test

without

slaves connected

) You can also check

the

CLK pin

with an oscilloscope

when you send

a byte

[dibs]

Posted on December 05, 2013 at 22:40

Thanks guys;

My original problems were twofold:The RXNE flag is delayed behind the TXE flag. I think that it should be by at least 1/2 the SCK period.Also, I found that if I stop by debugger (Keil) on the statement that checks for RXNE in the ISR, it always fails. But if I stop it after the if statement passes, then we are okay. 

[Tesla DeLorean]

Posted on December 06, 2013 at 02:55

TXE should assert quite early, as the holding buffer transfers to the shift register, RXNE should assert after the last bit shifts out, delayed by 1/2 a cycle where the data clocks in against the opposite edge.

The peripheral viewer will likely read the DR and SR, resulting in the clearing of RXNE

[dibs]

Posted on December 06, 2013 at 14:50

Okay, so let's say that I wanted to send out two bytes, and only view the return byte from the second tx. If I am putting tx data into the SPI-DR when TXE is set, will RXNE be already set immediately after I send the second byte? Would this cause an error where I would actually be reading the response from the first tx byte?