I am running out of SRAM on a project with an F407 and an investigating using an F427. My basic question is does anyone know of the issues with doing this? I have already read through the migration document (AN3364) and am continuing to investigate.I...

Posted on January 23, 2018 at 14:43Should the NRST external reset (PINRST) be set on an STM32F407 after a power reset?I want to be able to count the number of each type of resets in my code. The problem that I have is that the NRST pin reset is alwa...

Posted on October 16, 2017 at 21:08After enabling the hardware IWDG, I noticed that on subsequent SW programmings, I always get an immediate single IWDG reset event. After that reset, the system boots, but it seems to boot several times faster than ...

Posted on March 07, 2017 at 17:54I am working on a board (STM32F407VGTx) that has an older PHY chip KSZ8721BL. I have similar code running on the MCBSTM32F400 (v1.2) which has an KSZ8081RNA. In testing, I retrieved all of the registers from both PHY...

Posted on April 06, 2015 at 21:06I have a chain of 3 timers with TIMA -> TIMB -> TIMC.When TIMB is triggered it creates a pulse on an output pin via OPM. It then triggers TIMC to do an IC on its counter.What I want to do is to be able to programatic...