STM32F30x count external pulse Up/Down

[elettromanu]

Posted on March 06, 2014 at 14:40

Hi

,

I would like to

know

if is possible set

a timer

or other peripheral on the STM32F30x

to count

up or down

the pulses applied

to a pin

depending on the

logic level

applied

to a second

input

. For example if the second input is high the pulse are counted Up instead if the second input is low the pulse are counted Down.

I have carefully read

the

timer

section on the

reference manual

but have not found

how to set

the timer

to achieve this functionality

.

Please let me know. Thank you.

#stm32f30x

[elettromanu]

Posted on March 21, 2014 at 18:07

#1 I apply the clock at PA.6 configured as alternate function 2. Then the CCMR1 is configured for IC1-TI1. When I toggle the clock signal I see change the bit6 in PA IDR register so no hardware connection error happen. In this condition and with SMS=001 the count change (increment o decrement) instead RM0090 say ''Counter counts up/down on TI2FP2 edge''.

#2 the problem is not spurious count at startup but the counting direction that depend of the initial level of the clock signal.

Why

does it happen?

How do I

know

the internal state

?

This is may Main code and register value at runtime.

int    main(){

    //    FLASH->ACR     //     //     SystemCoreClock variable: Contains the core clock (HCLK) = 72MHz     //     //    HSE  = 8MHz     //    SYSCLK = 72MHz     //    HCLK = 72MHz     //     AHB = 72MHz     //    APB1 = 36MHz     //    APB2 = 72MHz     // CLOCK enable     RCC->AHBENR    |=         RCC_AHBENR_GPIOAEN +        // GPIOA clock                         0;     RCC->APB1ENR |=        RCC_APB1ENR_TIM3EN +        // TIM3 clock                         0;     RCC->APB2ENR |=        0 +        //                         0;     //-------------------------------------------------- PORTA                 GPIOA->MODER |=     GPIO_MODER_MODER1_0 +                        // PA.1 Out                         GPIO_MODER_MODER6_1+GPIO_MODER_MODER7_1+    // PA.6, PA.7 alternate Function Mode                         0;     GPIOA->AFR[0] = (2UL<<28)+(2UL<<24);                            // PA.6, PA.7 alternate Function 2     GPIOA->OSPEEDR |=     GPIO_OSPEEDER_OSPEEDR0 +    // PA.0 High Speed                         GPIO_OSPEEDER_OSPEEDR1 +    // PA.1 High Speed                         GPIO_OSPEEDER_OSPEEDR6 + GPIO_OSPEEDER_OSPEEDR7 +    // PA.6, PA.7 High Speed                         0;     GPIOA->PUPDR |=     0;     //-------------------------------------------------- TIM3     TIM3->CR1 = TIM_CR1_CKD_1/*+TIM_CR1_CKD_0*/;    // Clk digital filter 36MHz/4     TIM3->CR2 = 0;     TIM3->CCMR1 = (TIM_CCMR1_IC1F_0+TIM_CCMR1_IC1F_1+TIM_CCMR1_IC1F_2+TIM_CCMR1_IC1F_3) +    // Filter 36MHz/4/32/8=35KHz(28us)                     TIM_CCMR1_CC2S_0+TIM_CCMR1_CC1S_0;                                        // IC2-TI2, IC1-TI1     TIM3->CCMR2 = 0;     TIM3->CCER = 0;     TIM3->PSC = 1;     TIM3->ARR = 0x100;     //TIM3->SMCR = 0;     //TIM3->EGR = TIM_EGR_UG;     TIM3->SMCR = /*TIM_SMCR_SMS_3+TIM_SMCR_SMS_2+TIM_SMCR_SMS_1*/+TIM_SMCR_SMS_0+    //0001: Encoder mode 1                     0;             TIM3->CR1 |= TIM_CR1_CEN;     //TIM3->EGR = TIM_EGR_UG;          while(1){         int32_t k;         for (k=1000; k>0; k--)             ;                     SpareCounter32++;         GPIOA->ODR ^= GPIO_ODR_1;     } } Many thanks for your help.

[Tesla DeLorean]

Posted on March 21, 2014 at 19:03

#2 the problem is not spurious count at startup but the counting direction that depend of the initial level of the clock signal.

Why

does it happen?

How do I

know

the internal state

? I don't know, it's not how the functionality is described. The documentation for the TIM units is not particularly good, and the block diagrams lack detail. I'd prefer to see some more gate-level stuff, it would be less ambiguous. These TIM operations are somewhat outside my purview.