2023-03-27 05:47 PM
Hello!
I am trying to configure Master clock output frequency for I2S interfacing with the TI tlv320aic3254 but there is no Master clock or i2s setting on the clock configuration.
As i see in the Clock tree in the datasheet there are master clock options with pll multiplier selection. I need to configure the sampling frequency to 48khz and it doesn't let me because of the low clock speed and the 0 divider value!
Thanks for the help!
Best regards
Pantelis
2023-03-28 01:13 AM
The 48-pin package does not have PC9=I2S_CKIN, so in that package the only option is to clock I2S from system clock.
So, you have to set up system clock so that it's the required multiple of WSCK frequency. I don't know how did CubeMX arrive at 43MHz, read the I2S chapter to determine what input clock frequency you need.
You will need to use PLL, and if your application is audio, HSI is probably an inadequate primary clock source as it's not stable enough for audio applications.
JW
2023-03-28 06:19 PM
Hello!
I did some research and testing and i noticed that although there is no way to put sampling rate to 48khz through the .ioc pin configurator if i set hi2s2.Init.AudioFreq = I2S_AUDIOFREQ_48K; through the MX_I2S2_Init, the sample frequency changes with respect to the masterclock because the datasheet states that MCLK frequency is fixed to the sampling Frequency*256 which is in fact true because i checked it with my osciloscope. The mclk frequency is bigger if i set hi2s2.Init.AudioFreq = I2S_AUDIOFREQ_48K!
Now the problem i have is that although i configure the master clock deviders of the tlv320aic3254, i have the correct i2s clocks and i see data coming out of the codec into the mcu, HAL_I2S_Receive writes nothing to the buffer...:crying_face:
First shows master clock with hi2s2.Init.AudioFreq = I2S_AUDIOFREQ_8K
First shows master clock with hi2s2.Init.AudioFreq = I2S_AUDIOFREQ_48K
If thats the case i dont know why sample frequency can not be change through .ioc pin configurator.
Best regards
Pantelis