2012-12-12 07:35 PM
Hi,
I successfully setup IAR 6.5 and got the F3 Discovery Bd. demo working along with modifying the code to change the LED timing. I read through UM5170 User Manual. I'm looking for more examples to learn about the peripherals. So, I downloaded the AN4157 firmware examples. This includes brief descriptions of each peripheral but not the tutorials to work them.I also found examples with, ''This example has been tested with STMicroelectronics STM32303C-EVAL (STM32F30x) evaluation board and can be easily tailored to any other supported device and development board.'' However, it doesn't explain How to do this.Since I'm new to ARM and 32F3, I would appreciate what next steps to learn this platform.Thanks! #stm32f3-iar #adc #discovery-board #:-discovery-board-stm32f32013-09-30 07:03 AM
And what do you think about 1),2) and 3)? is correct as configuration ?
''You could process the data in place if you are capturing and stopping, or you could upload the data and post-process it.''
When upload data, i'll have the limitation resources problems but what do mean by capturing and stopping ?2013-09-30 08:22 AM
This is your project, you'll need to make your own determinations.
Capture and Stop, ie you capture at a rate the maximum amount of data, then stop capturing, and process the data you have. Where the capture rate is higher than the rate you can process the information. Discontinuous. Snap-Shot2013-09-30 08:58 AM
Ok, thanks you, by my question about computing values i was asking if it's the correct method or no.
Your explanations were very helpful for me to understand a lot of thing, i'll be an expert of STM32 :) thank you again2013-09-30 10:03 AM
i was asking if it's the correct method or no.
The numbers aren't making much sense to me, if I wanted to sample at 100 KHz I wouldn't pick a sample time that's slower (>180 cycles), and I'd expect the TIM to initiate conversions at 10 us not 100 us. The conversions aren't pipelined, so you'd also want some amount of margin too. I'm saying that you need to do the long/hard thinking about this. I'm not using the F3/ADC and not looking to get pulled into intricacies of the documentation/function at this level.2013-10-18 07:03 AM
Hi again clive1,
So i succeed to get my 4 ADC working together in the same time. But i still have problem. When i drive the same input for ADC1 and ADC2 working in dual mode, sometimes i don't have the same value for the slave and the master, i have noticed that looking at the CDR register in debug mode. The same problem with ADC3 and ADC4.Enclosed
you will find
the code i have used. If will be very grateful for any help. Remark: The same input is driver to the 4 ADC to test if you get the same output at the same time. ________________ Attachments : main.c : https://st--c.eu10.content.force.com/sfc/dist/version/download/?oid=00Db0000000YtG6&ids=0680X000006Hzow&d=%2Fa%2F0X0000000bQ9%2FOaHX5E1q6HBQaWryJKw1nam5DWGMWoz2CsD09RLUInI&asPdf=false2013-10-18 07:35 AM
sometimes i don't have the same value for the slave and the master
The value is not identical, or the difference is bigger than some expected conversion error threshold?2013-10-18 09:05 AM
The value is not identical, or the difference is bigger than some expected conversion error threshold? : Difference sometimes is bigger than the expected conversion
2013-10-18 12:49 PM
Ok, I'm not sure if that quantifies it for me.
A bigger issue here might be one of memory coherency, the ADC+DMA operation is continuing concurrently with the CPU. You are reading values that can be transient. You might want to be using the HT and TC interrupts and processing the half the buffer at a time in a ping-pong fashion. If you plan on dwelling on the data for a while, you might want to memcpy() it to another buffer which doesn't have DMA going on in the background. Ideally you will process the data at a rate faster than the ADC is generating it.2013-10-22 08:41 AM
2013-10-22 09:12 AM
For most purposes the two DMA operations are occurring in parallel. For coherency you want to be using the HT and TC events to process half of the buffer for both groups of samples.