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STM32F2 ADC Signal Noise

mbleha9
Associate III
Posted on October 28, 2011 at 12:00

I have just tested my second design with STM32F2, now it is STM32F207ZFT6, the ADC behaviour is the same as in my first application - strong noise in ADC signal.

Essential part of the board schematics :

http://www.sendspace.com/file/si46gl

Board photo :

http://www.sendspace.com/file/45n68v

Noise of  current input without any signal connected : 

http://www.sendspace.com/file/totkwn

The same input noise with the CPU analog pin shortcircuited to GND : 

http://www.sendspace.com/file/cjagfy

Note : In the signal graphs above,  the vertical axe is in ADC-bits, not in volts!

; don�t be confused by its legend �[V]�, for this test we have used our modified program to see rough ADC data.

There are permanent spikes over 30 LSBs and more in the sampled signal, although they shouldn�t exceed 5-10 LSBs, by my opinion.

Another details :

  • 2-side PCB, on the bottom side there are another connections but most of it is poured with GND signal - common for both digital and analog, the analog ground is not separated. As the board consumption is minimal, below 100 mA,  I think it should not cause such noise.

  • voltage reference VREF 3.3V buffered by opamp, blocked by 100nF and tantallum 10uF in parallel, the same with VREF/2;  each of the processor power pin is blocked with 100nF cap

  • in our older application we used the same design concept, but the processor used was AduC834; it has 12-bit ADC too and the signal noise was several LSBs only, there were no problems; main difference was that the AduCs internal voltage reference was used, no external one
  • we have tested to disconnect processor analog ground pin from the board common GND and to connect it with extra wire directly to the voltage reference VREF ground, no effect
  • it is three-phase network measuring device, there are 3 analog voltage channels and three current channels with switchable gain preamplifier; the CPU oscillator 25 MHz, internal clock 120 MHz by PLL, ADC-clock is 30 MHz(in compliance with techspecs), we have tested to slow main internal clock (therefore all secondary clocks too) downto one quarter, but without any effect
  • ADC samples periodically input signal with rate 128 conversions per 50 Hz network period, i.e. each 156 usecs; results are transferred by DMA into internal RAM; data from the RAM are transferred via insulated RS485 (on another board) and visualized in our program. We have tried to prolong conversion times to maximum, no effect
  • excluding CPU, there are only

    3 opams, 2 analog switches, I2C thermometer and three  ULN-switches(unused during test), powered by linear LF33 stabilizer, normally powered by 5V DC from switcher on another board, but during the test the switcher was disconnected and the LF33 was powered from clear laboratory 5V DC supply. I am sure nothing but the processor oscillator can oscillate on the board.

  • checking  the signal with oscilloscope doesn�t get decisive results, the signal is too weak

 Anybody with this processor family ADC performance experience

?

#stm32f2-stm32f4-a/d-noise #adc-noise
27 REPLIES 27
mbleha9
Associate III
Posted on February 06, 2012 at 11:02

Thanks, Werner. But I have already redesigned my PCB to four layers. As soon as new sample will be ready I will write what is new. I still hope it is matter of PCB design and I will not need to switch to another chip.

But if you have real experience with NXPs or others ADCs immunity/precision on two layer PCBs, it would be worth considering ...

emalund
Associate III
Posted on February 06, 2012 at 15:31

Noise immunity is NOT a chip selection issue it is solely, singularily, only a layout issue.

Erik

emalund
Associate III
Posted on February 06, 2012 at 17:17

In addition,

just going to 4 layers is not enough, short traces, careful decoupling, clean supply, .... is also required.

Erik

aage
Associate
Posted on February 22, 2012 at 06:21

I have also been seeing more than expected noise on the A/D input measurements on the SM32F207VET and STM32F407VET.

I am seeing noise span of 20 to 30 counts.

I have one A/D input which runs parallel for about 40mm with an spi mosi signal it. That input had a noise span of about 80 with the spi running. Turning the spi off the noise span dropped to the ''standard'' noise span of 20 to 30 counts.

And on the internal temperature measurement I am seeing a noise span of typically 15 to 16 counts.

The noise on the internal temperature sensor is interesting to me as a reference, since there isn't any external signals to it, except the reference supply and power supply.

Does anybody else have the noise span for the internal temperature sensor.

mbleha9
Associate III
Posted on July 19, 2012 at 13:55

Finally, I have the new 4-layer PCB ready. And - what surprise - the noise is off  ! Only standard noise of several LSBs corresponding to techspecs remains, of course.

The PCB is designed according the Franks link above, i.e. no crossing of analog traces with digital ones. Grounds are separated to GND and AGND and connected together at the CPU analog ground pin. Internal layers fully poured and connected to ground and +3.3V.

Thanks all for help.

emalund
Associate III
Posted on July 19, 2012 at 14:49

Finally, I have the new 4-layer PCB ready. And - what surprise - the noise is off  !

 

no surprise

Erik
mgagliarducci9
Associate
Posted on March 29, 2016 at 08:49

Hi Milan,

the silicon revision of STM32 is the same on two pcb?

Posted on November 20, 2017 at 03:38

Can you share your PCB design. My email:

mailto:vixuanthanh93@gmail.com

 I follow you post but I dont know how to design pcb to make noise off. I test stm32f4 read analog by plug resistor, and result not corect, noise height. Thank you so mutch.