STM32F103 - PB3 just doesn't work as GPIO

[tilmann]

Posted on December 14, 2016 at 10:27

Hello,

did anyone ever manage to get PB3 working as an I/O port on an STM32F103?

I am having a hard time with the F103VB where I need PB3 as input - no matter what I try, PB3 simply is returning a 0 value.

AFIO->MAPR is set to SWD debug only, JTAG off (and AFIO clock is on, of course).

I also explicitly set DBGMCU_CR to turn TRACE off, although that should be default after reset.

The other two related port pins (PB4 and PA15) work perfectly fine as GPIO. Only PB3 simply appears dead.

The errata sheet also doesn't mention any problems with PB3 as GPIO.

Did I find a new bug?

Any help is greatly appreciated.

Thanks, Tilmann

[Chris1]

Posted on June 01, 2017 at 18:16

Perhaps mode should be GPIO_Mode_Out_PP.

[markus-muc]

Posted on June 01, 2017 at 20:22

I just realized I was wrong with PB4, it is stuck at high and also does not switch. AFIO clock is enabled, I will check later for the 

DBGMCU_CR ...

[markus-muc]

Posted on June 01, 2017 at 18:36

Tried this as well - it doesn´t change anything. PB4 works but PB3 doesn´t - whether mode is 

GPIO_Mode_AF_PP or 

GPIO_Mode_Out_PP seems to be don´t care.

[markus-muc]

Posted on June 01, 2017 at 18:37

I still think it has something to do with 'asyncronous trace', but I don´t know how to make sure with Atollic to have it disabled. Maybe somebody can help?

[Tesla DeLorean]

Posted on June 01, 2017 at 18:42

Make sure the AFIO clock is enabled, heck enable the clocks early so you don't have to fight order of initialization and interaction battles you don't need too.

[waclawek.jan]

Posted on June 01, 2017 at 18:48

Read back content of DBGMCU_CR - is TRACE_IOEN set?

When at it, read also all relevant GPIO and AFIO registers and check their content.

JW

[_dalbert]

You can indeed use PB3 and PB4 as GPIO pins provided you do not need their default TRACESWO and NJTRST functions (which you don't for most ST-Link V2 debugging). The following code is tested and works.

    // Release PB3/TRACESWO and PB4/NJTRST from control of the
    // Debug port so they can be used as GPIO pins
    DBGMCU->CR &= ~DBGMCU_CR_TRACE_IOEN;
    RCC->APB2ENR |= RCC_APB2ENR_AFIOEN;
    AFIO->MAPR |= AFIO_MAPR_SWJ_CFG_JTAGDISABLE;

[_dalbert]

Agreeing with Clive: this isn't true, you do not need to disable SWD. You want option 2 (SWJ_CFG=010 -> JTAG-DP Disabled and SW-DP Enabled) in the above table. I use PB3 and PB4 as GPIO with SWD enabled.

[_dalbert]

There's no bug, I use PB3 and PB4 as GPIO while using SW-DP. I've supplied the configuration code to release PB3/PB4 from the debug port later in this thread.

[Tesla DeLorean]

Which is what I indicated 2+ years ago to refute the "If you want to use PB3 pin, you must also disable the SWD." assertion of the poster.

And I responded "That really isn't what the RM0008 manual says... DIAGRAM"