2023-02-17 09:41 PM
Hello all,
I'm trying to communicate with SRAM device on my board.
I'm using STM32H747XIH6 MCU.
I tried to capture the Write enable, chip select and output enable pins on the board but I saw an unusual response of the output enable.
My configuration for the SRAM is as follows
/** Perform the SRAM2 memory initialization sequence
*/
hsram2.Instance = FMC_NORSRAM_DEVICE;
hsram2.Extended = FMC_NORSRAM_EXTENDED_DEVICE;
/* hsram2.Init */
hsram2.Init.NSBank = FMC_NORSRAM_BANK2;
hsram2.Init.DataAddressMux = FMC_DATA_ADDRESS_MUX_DISABLE;
hsram2.Init.MemoryType = FMC_MEMORY_TYPE_SRAM;
hsram2.Init.MemoryDataWidth = FMC_NORSRAM_MEM_BUS_WIDTH_32;
hsram2.Init.BurstAccessMode = FMC_BURST_ACCESS_MODE_DISABLE;
hsram2.Init.WaitSignalPolarity = FMC_WAIT_SIGNAL_POLARITY_LOW;
hsram2.Init.WaitSignalActive = FMC_WAIT_TIMING_BEFORE_WS;
hsram2.Init.WriteOperation = FMC_WRITE_OPERATION_ENABLE;
hsram2.Init.WaitSignal = FMC_WAIT_SIGNAL_DISABLE;
hsram2.Init.ExtendedMode = FMC_EXTENDED_MODE_DISABLE;
hsram2.Init.AsynchronousWait = FMC_ASYNCHRONOUS_WAIT_DISABLE;
hsram2.Init.WriteBurst = FMC_WRITE_BURST_DISABLE;
hsram2.Init.ContinuousClock = FMC_CONTINUOUS_CLOCK_SYNC_ONLY;
hsram2.Init.WriteFifo = FMC_WRITE_FIFO_DISABLE;
hsram2.Init.PageSize = FMC_PAGE_SIZE_NONE;
/* Timing */
Timing.AddressSetupTime = 6;
Timing.AddressHoldTime = 15;
Timing.DataSetupTime = 12;
Timing.BusTurnAroundDuration = 3;
Timing.CLKDivision = 16;
Timing.DataLatency = 17;
Timing.AccessMode = FMC_ACCESS_MODE_A;
/* ExtTiming */
if (HAL_SRAM_Init(&hsram2, &Timing, NULL) != HAL_OK)
{
Error_Handler( );
}
The captured waveform is attached belowBlue : Write Enable
Yellow : Chip Select
Pink : Output enable.
I do not understand why does the output enable toggle multiple times for one write/read operation.
2023-02-17 11:28 PM
Cortex-M7 are complex. Do some background reading.
How is this area defined in MPU?
Reads to Cacheable areas result in cache line fill, read to non-cacheable but Normal areas are subject to speculative prefetch.
JW