spi slave weird data on mid-high speeds ?!

[arhi]

I am having weird issue with STM32F767 (configured to run at 200mhz) that needs to be SPI slave .. I configured it with 0,1 (clock low, second edge), hardware cs.. when master sends data at 350kbps everything is ok, when master sends at higher speeds output is random (like bits are swallowed).

code is super simple just hal_spi_transmitreceive() in a loop sending 2 same bytes non stop

it behaves like hardware can't catch up and start sending data late and slower than the clock...

[AScha.3]

>looks like some phantom clock is happening

maybe ringing ...try a damping R , 75 ohm in the clk line ; before + after adum.

i had a big problem with a fpga and its 50MHz clock, just close, 15mm track.

sometimes work, sometimes crazy errors.

after days (!) i tried a 50 r inserted here - and runs perfect then. unbelievable. 

[arhi]

we planned to add resistors to test but when I look signals under scope I do not see any issues .. and also at 400khz at few mm I do not see htf can any ringing happen but.. after all the @#$()&^@ on this project I can believe anything at this point... wasted weeks on something that was in reality 2-3 hours of work all 'cause of pcb issues

[TDK]

Really can't imagine this is a PCB/interference issue at 400 kHz if the chips are 10 mm apart.

You have some weird bounce happening on the clock. Initial edge is super sharp, but then it bounces back and goes slowly to the rail. Could be a miscalibrated scope.

Also think sending a better pattern would be useful. Perhaps 0x0102, and the inverse, and post it here.

[David Littell]

Connect the SPI Slave MCU's NRST to the logic analyzer (in addition to the SPI signals you already have) and set the logic analyzer to trigger at the rising edge of NRST.  Have the analyzer record for long enough to include your 2-byte test sequence.  Look for a condition in the trace where CS is asserted (low) and there are some (spurious?) clocks on SCK before your 2-byte test sequence.  Have the logic analyzer display its analog channel for CS and SCK in addition to the digital channels.

Also, can the isolator be temporarily removed from the circuit?

[arhi]

I tried different patterns, all look like there is phantom clock happening... I'll do more imaging and will upload later today ... I'm attm writing the sw on the working board with different stm so I can finish the sw part before I come back to solving this mess

as for "can't imagine this is a PCB/interference issue at 400 kHz if the chips are 10 mm apart." ... it is hard to imagine how bad pcb can be... our post is in strike for few months so can't order anything so we made it in-house and changed whole bunch of things after the fact so now it looks... well ..

 

[arhi]

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@David Littell wrote:

Connect the SPI Slave MCU's NRST to the logic analyzer

hm, but nrst is controlled by the debugger (segger j-link in this case) how that relates to spi, and when the mcu is started nrst does not change??

> Look for a condition in the trace where CS is asserted (low) and there are some (spurious?) clocks on SCK before your 2-byte test sequence.

oh yes

> Have the logic analyzer display its analog channel for CS and SCK in addition to the digital channels.

unfortunately the LA with analog input working is not with me (I moved recently to new house+lab and most of my tools are not with me ) and the digital cable for my 4ch scope that has integrated LA is also not with me so can't do it these days but I understand the idea, thanks

> Also, can the isolator be temporarily removed from the circuit?

ah that would be the first thing to try if I could but my eyesight is going haywire so any changes on the pcb I need to call someone to do it so it takes a lot of time and I'm afraid this pcb can't take much more abuse I think it is time we make a completely new one and transfer the mcu... additional issue is we do not have enough mcu's and can't order more... this whole project is .. uh.. anyhow, great ideas, I have bunch of things to test now

[TDK]

That looks awesome. I'm sure you guys had fun making it.

[arhi]

hahahah yeah, my type of sarcasm ... fun ... the story about this project is one of the worse in my career everything that could go wrong went wrong ... i started to doubt my basic knowledge about electronics with this project... but .. we'll get there

[David Littell]

Why did you not start with a Nucleo and just design a board to plug in?

[arhi]

getting anything these days is super hard but nucleo with 676 (Nucleo-144) is not available anywhere, lead time is in hundreds of weeks and looks like ST stopped making them altogether so .. we would but .. at least we would use nucleo-144 for development instead of these ugly things but we used our last nucleo-144 on our previous project where we had to use our nucleo boards as we could not purchase chips anywhere as they were out of stock ...