SPI signal distorted at high speed

[JCAeron]

Two STM32H743 series MCUs are on a single board and they communicate using SPI. When SPI clock frequency is more than 1.5 Mhz, SPI communication is not working properly. The distorted clock signal waveforms at high frequencies are attached below.

A 51E series resistor is connected on all 4 signals.

The trace length is almost 35mm

I tried reducing the series resistors from 51E to 33E and 20E. No much difference was observed in the waveforms. What can be done? 

1. CLK freq = 1.5MHz

2. CLK freq = 3.125MHz 

3. CLK freq = 6.25MHz

4. CLK freq = 12MHz

[waclawek.jan]

Set the SPI's CLK and MOSI (and MISO in slave) pins to higher speed on their respective GPIO_OSPEEDR register fields.

JW

[AScha.3]

Yes, set pin speed in Cube -> very high , as @waclawek.jan  said.

And your probe (-> DSO) set to 10:1 ? ( otherwise probe cap. load too high .)

[JCAeron]

Please see the attached image. That seems to be already done.

 

[JCAeron]

Hello @waclawek.jan @AScha.3 

Any update on what can be done? 

[waclawek.jan]

Theres not much to be done. Either is the line heavily capacitively loaded (e.g. by inadvertently being shorted to some neighbouring pin), or it is driven incorrectly.

You can ultimately check the latter by reading out and checking content of relevant GPIOx_OSPEEDR register e.g. in debugger.  You can also try to *decrease* the speed to see whether it has the expected effect. Also check if compensation cell is switched on properly.

You may also experiment with disconnecting the resistor entirely.

I don't use the 'H7 line. You may also want to check the datasheet and/or errata for possible deviation of this particular pin.

JW

[AScha.3]

Still no answer to:

And your probe (-> DSO) set to 10:1 ? ( otherwise probe cap. load too high .)

[JCAeron]

Yes I checked it with the probe set to 10x.

This is the output waveform of CLK signal set at 12MHz. The DSO reads it to be around 6.25MHz. I used a 330 ohm series resistor to remove ringing. And this is the observed output. 

[waclawek.jan]

> This is the output waveform of CLK signal set at 12MHz. The DSO reads it to be around 6.25MHz.

Then it's around 6.25MHz and the clocks setup in STM32 is not what you think.

> ... ringing

Often, the problem is ground arrangement, but it can also be simply caused by improper probing (ground pigtail on the scope probe, and its placement).

> SPI communication is not working properly

However, even if this ringing would be a genuine artefact of the signal, this amount of ringing is probably not the cause of your original problem. Try to describe what are your observations.

JW

[AScha.3]

10:1 probe :ok.

>What can be done here ?

Improve your skills in the field of measurement technology, especially measurement of fast signals .

see:

https://www.analog.com/en/resources/analog-dialogue/articles/hgh-speed-time-domain-measurements.html