SPI problem with hardware NSS management

[mudrovc]

Posted on October 26, 2009 at 04:22

SPI problem with hardware NSS management

#stm32f0 #metoo-maybe #nss #dma #spi

[ericbrocke9]

Posted on May 17, 2011 at 12:38

Sorry guys but you should better read the manual as pointed out by STOne-32!

The manual (RM0008 rev 5) says on page 541: ''NSS output is enabled: when the STM32F10xxx is operating as a Master and the NSS output is enabled through the SSOE bit in the SPI_CR2 register, the NSS pin is driven low and all the NSS pins of devices connected to the Master NSS pin see a low level and become slaves when they are configured in NSS hardware mode.'' The NSS pin is mentioned as a select pin to activate the interface in slave mode (yes! NSS -> Not Slave Select. Surprised?). Eric p.s. The normal situation is a single master with multiple slaves which then requires a NSS line for each slave. The master has to select a specific slave which cannot done by one NSS pin. [ This message was edited by: eric.brocke on 06-08-2008 21:10 ]

[slawcus]

Posted on May 17, 2011 at 12:38

But the issue about NSS is that it is set low just for the first time SPI is used and then it stays low until disabling SPI peripherial as I described.

One should expect that after master stops sending data NSS will go high. What does it mean ''become slaves''? Is this multimaster SPI situation and if other masters see the low level on their NSS they go to slave? How should ''first time'' master become a slave if its NSS pin is at low level all the time? P.S. As stated in user manual multimaster mode is not supported if NSS output is enabled. I really don't understand what is the purpose of NSS hardware mode. If one device is configured as master and other as slave why would slave become slave? [ This message was edited by: slawcus on 06-08-2008 22:57 ]

[roger7]

Posted on May 17, 2011 at 12:38

As stated in user manual multimaster mode is not supported if NSS output is enabled. I really don't understand what is the purpose of NSS hardware mode. If one device is configured as master and other as slave why would slave become slave?

Don't worry. I am as confused as you're. Having worked with many MCUs and SPI, this STM32 HW treatment of SPI I/F is mind numbing, especially if it is not consistent - documentation vs. performance. But it is still too early to get the bugs out of silicon, I suppose. Something got lost in translation

[swsyah]

Posted on May 17, 2011 at 12:38

I've run into the same problem. I have a single slave and it would be nice to have the STM run the NSS as a CS automatically.The reference manual shows a timing diagram that seems to indicate it can do this, but I can't find a combination that does it. The writeup is not clear.

[slawcus]

Posted on May 17, 2011 at 12:38

Anyway, this NSS driving thing shouldn't have much impact on performance. Semi-automatic handling can be done with irq routine which is called after the end of transmition (even for DMA transfers).

[gdp123a]

Posted on May 17, 2011 at 12:38

I agree with SWSYAH - it would be nice to have the STM run the NSS as a CS automatically. I originally thought this was the purpose of the NSS pin. The reference manual is not clear (in regards to the NSS) and it was only by running test code that I discovered the sad truth,

Greg.

[i239955_st]

Posted on May 17, 2011 at 12:38

Hi,

Is there any news with this issue ? I'd like to use DMA to tranfer massive data to DAC with automatic chip select managment. This feature works on atmel, why this seems not to be available on much complex STM32 ? bad news for my project. I think a workaround could be to synchronize a timer to automatically valid each SPI frame. What do you think : is it risky ? What a pity to be constrained to do that...

[jj]

Posted on May 17, 2011 at 12:38

Hi STOne-32:

Perhaps the new year is a good time to ''re-seek'' your assistance in enabling the STM32 to provide a hardware (automatic) generation of the NSS-CS. Most all of my clients and ''every'' engineer/programmer attendee at the four STM32 seminars I've joined ''want'' this. Doing it in software slows the process and is unwieldy. It is annoying that so many (most ALL) lesser micros ''do achieve'' hardware/automatic generation of NSS-CS. Thank you for your interest & great assistance - I know that many would appreciate ST's converting NSS-CS to this much more standard, ''hardware/automatic'' NSS-CS generation... {note further - nearly 2000 views of this topic ''prove'' the seriousness of automatic NSS-CS!) [ This message was edited by: jj.sprague on 26-12-2008 17:45 ]

[16-32micros]

Posted on May 17, 2011 at 12:38

Dear jj.sprague,

Thank you so much for your interest ! I will escalate this Request feature for Analysis then if required to our ''wish-list'' so we can take into account this valuable feedback to our next future products. Wish you a Happy New Year 2009 🙂 Cheers, STOne-32. [ This message was edited by: STOne-32 on 26-12-2008 18:53 ]

[jj]

Posted on May 17, 2011 at 12:38

Dear STOne-32,

Thank you - great news! Automatic NSS-CS is important to many... Wonder if we forum users could assist you by listing our top ''three'' STM32 ''suggestions?'' (seems like a new thread makes sense - if you like this idea.) Again - clients, engineering associates, university contacts ALL Love this forum! Thank you again for your hard work in our behalf... Happy New Year to all... Regards, JJ