Posted on May 17, 2011 at 12:41Here is a code snippet to do the job: static u32 rbit(u32 d) { __asm__ ( '' rbit %0, %0'' : ''=r'' (d) : ''0'' (d) : ''cc'' ); return d; } void foo(void) u32 *p, crc32; p = ...; Crc.CR.bit.RESET = 1; while (...

Posted on May 17, 2011 at 12:41Hi STOne-32, You are right about the reset value. I'd make a mistake about reading the value after enabling the CRC clock. What abbout the first CRC issue? Thanks, Eric.

Posted on May 17, 2011 at 12:41Addition: The reset value of the CRC_DR is 0xFFFFFFFF and not 0x00000000 as mentioned in the Reference Manual (RM0008 Rev 5).

Posted on May 17, 2011 at 12:41I'm using the CRC calculation unit and it seems that the result of the data register (CRC_DR) is bit-reversed and bit-wise inverted. Entering 0x00000000 gives 0xC704DD7B as result which should be 0x2144DF1C (using srec...

Posted on May 17, 2011 at 12:38Sorry guys but you should better read the manual as pointed out by STOne-32! The manual (RM0008 rev 5) says on page 541: ''NSS output is enabled: when the STM32F10xxx is operating as a Master and the NSS output is ena...