SPI not working with STM32L476VG Discovery Board?

[JDarg]

We are using the STM32L476VG Discovery Board and are trying to use the SPI 1 interface. I generated the code through CubeMX with pins PA5, PE13, PE14, PE15. After the code was generated I tried placing this example code into the while loop:

    HAL_GPIO_WritePin(GPIOA, GPIO_PIN_4, GPIO_PIN_RESET);

    HAL_SPI_Transmit(&spi, (uint8_t *)message, strlen(message), HAL_MAX_DELAY);

    HAL_GPIO_WritePin(GPIOA, GPIO_PIN_4, GPIO_PIN_SET);

    HAL_Delay(10);

I then run the code through TrueStudio Debugger and I can't see a clock signal with an oscilloscope. I have also tried different variations of that above code with Hal_TransmitReceive. Is there any example SPI code meant for the STM32L476VG Discovery Board? Am I missing a step after I generate the code with CubeMX?

Thanks!

[S.Ma]

Have you done a SW breakpoint after launching the code and look at the SPI HW register and GPIO setting? Just in case. Also on the schematic, no conflict for these pins?

You can manually run the SPI by editing its HW registers (DR) and see if the non SW related stuff works.

[JDarg]

Thanks for the quick reply. I added a screenshot of the SPI HW register after init.

I did not see any conflict. I set it up with CubeMX also so I think that would have caught conflict. The code I'm trying is very simple and does not involve any other interfaces. What should I expect if I change the HW registers?

[S.Ma]

Check GPIO MODER for the corresponding pins.

Also make sure you try it out with SW NSS and set the SW NSS bit properly.

Example of setup:

IO_PinConfigure(&CLK_PIN); // PB3 = SCK3
IO_PinConfigure(&DO_PIN);  // PB5 = MOSI3 (bidir)
IO_PinConfigure(&DI_PIN); // PB4 = MISO3 (no use)
  
  __HAL_RCC_SPI3_CLK_ENABLE();  // Enable SPI2 clock
  SPI3->CR1 =  0//     (1<<15)  // bidir = 1 
                //  | (1<<14)  // TX mode, output enabled 
                  | (1<<9) // SSM=1
                  | (1<<8)
                  | (1<<7)   // LSB first 
                  | (0<<3)   // prescaler div1 = 24 MHz
                  | (1<<2)      // master mode
                  | (0<<1) // SCK is low when idle
                  | (1<<0); // the second clock edge is the data capture's
 
  SPI3->CR2 =       (0<<12) // RXNE when 8+bit in FIFO
              |     (7<<8); // 8 bit mode (n-1)
 
  SPI3->CR1 |= (1<<6); // SPI enable
 
 

Just to check if the NSS is proper. If not, the IO might be HiZ as "not selected".