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SPI Burst mode - Maybe?

shingadaddy
Senior

Hello St Forum! Good to be back at it for another little project here. 

Good to see familiar names.

SPI 

Going to try and match up an STM32l476VG using SPI to a Ethernet widget. Widget says it can use SPI and apparently it (widget) will auto increment address for storage/reading of incoming/outgoing bytes by simply continuing the SCLK! 

Example:

send 4 DATA bytes to sequential addresses in widget by :

32 clocks ( containing, for this device, MODE BYTE for READ/WRITE, 2 address bytes and a DATA BYTE)

Then 8 more clocks and data bits and data bits get shoved to the next address in widget

Do that 2 more times and --- you've send 4 bytes!

Hopefully I understood *THAT* like it was meant.

Burst mode maybe?

Not Googled it yet. Obviously I value here more than Google 🙂

Many acronyms and buzzwords with SPI. Especially from various different manufactures and a LOOSE spec! 

I see in the 476 RM timing diagrams, that the SPI1,2,3 channels *LOOK* like they will do this 8 bit data size "multiple data byte" or 16 bit data size "multiple data word" trick with following clock, but the words in the manual don't paint a clear enough picture for me.

Might make handling the data a little precarious but could be handy.  

I've used this micro to talk with MAX6966's with the simulataneous "Full duplex" in / OUT AT THE SAME TIME trick. That was some juggling!

I'll probably start hosing down the widget with a stream of bits tomorrow.

Anything I'm well off track on, please just nudge me around a little!

Good to see you folks again.

1 ACCEPTED SOLUTION

Accepted Solutions
Scott Löhr
Senior II

Every Widget datasheet I've worked with used the term "SPI burst mode" to refer to writing more than 1 byte of data per sequence of "CSnot line low, Transmit setup like Mode byte, Address byte(s)", then "burst" N-bytes, then CSnot line high. The ST sample apps clearly show configuring a SPI for 8-bit mode, so you're done before you've even begun 😉

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2 REPLIES 2
Scott Löhr
Senior II

Every Widget datasheet I've worked with used the term "SPI burst mode" to refer to writing more than 1 byte of data per sequence of "CSnot line low, Transmit setup like Mode byte, Address byte(s)", then "burst" N-bytes, then CSnot line high. The ST sample apps clearly show configuring a SPI for 8-bit mode, so you're done before you've even begun 😉

shingadaddy
Senior

Thank you Scott! Yeah code seems to indicate that, and the timing diagrams. I'm however *SCOPE LIMITED* by my past few applications of SPI ( that I can remember anyway) . Mostly flinging out bits to a few offerings of I/O expander chips here and there. 8 or 16 bits was all it took! One and done so to speak, for READING or WRITING.

I looked for the word "Burst" in the RM. It comes up in the flexible memory controller and DMA related sections. BUT --- nowhere in the SPI section.

:\

My luck shining through there.

Hm. Well I've been gone from here for long enough and the forum has definitely changed over time, so I've LOST ALL MY POINTS!

Both Clive and Jan warned me before about being too loose with frittering my points away! Now I'm just a "squid" again.

Response Much appreciated!