Slave timer configuration procudes an interrupt STM32f10x

[JJohn.3]

int Pulse(void)
 
{
 
TIM_TimeBaseInitTypeDef     TimeStruct; 
 
 
            RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM2,ENABLE);
 
    
 
            TIM_SelectInputTrigger(TIM2,TIM_TS_ITR3);//     
 
            TIM_SelectSlaveMode(TIM2,TIM_SlaveMode_External1);
 
 
            TimeStruct.TIM_Prescaler=0;
 
            TimeStruct.TIM_CounterMode=TIM_CounterMode_Up;
 
            TimeStruct.TIM_Period=29;
 
            TimeStruct.TIM_ClockDivision=TIM_CKD_DIV1;
 
            TimeStruct.TIM_RepetitionCounter=0;
 
            TIM_TimeBaseInit(TIM2, &TimeStruct);
 
            TIM_ITConfig(TIM2,TIM_IT_Update,ENABLE);
 
    
 
        ///Master Configuration code
 
...
 
 
 
}
 
 
void TIM2_IRQHandler(){
 
 
   if (TIM_GetITStatus(TIM2, TIM_IT_Update) != RESET)
 
   {    
 
    x=x+1;   
 
    TIM_ClearITPendingBit(TIM2, TIM_IT_Update);
 
   }
 
    
 
}

I am going to config a master and slave configuration under STM32f10x. I connected them correctly but at the first step it generates an interrupt before enabling the master timer or enable the slave timer. Here is my code:

after calling the Pulse function, it generates TIM2 interrupt(x=1), I need to know why it generates an interrupt when its trigger source is not configured/enabled.

[waclawek.jan]

This is consequence of the called library setup function setting TIMx_EGR.UG.

JW

[JJohn.3]

Thank you very much, it works fine, could you let me know about the role of this (EGR) register?does it mean every time that I changed the PSC or counter it makes an interrupt?

[waclawek.jan · Accepted solution]

No, setting PSC or CNT alone won't cause interrupt. It's every time you (and by "you" I here mean also "the library function you are calling") set TIMx_EGR.UG, it sets the Update flag (which can cause interrupt if enabled).

The "library" function does it because setting PSC won't change the prescaler immediately, as PSC is preloaded. Read the TIM chapter in RM.

JW