Solved
SAI / I2S w/ multiple sampling rates & Audio Clock Input (I2S_CKIN)
In all the STM32s that have I2S / SAIs and ethernet that I've checked, there is this fixed oversampling ratio of 256 between master clock and sampling rate.
When using the internal PLL to get the sampling clocks, no problem (amazing how good and stable these clocks are, even with the 8 MHz from the STLink, checked it with generating 24bit/192k SPDIF signals).
But in my case I must use the extra "Audio Clock Input (I2S_CKIN)", which does not have the benefit of getting modified by a PLL.
So my problem now: how do I get 3 different sampling rates (e.g. 48k / 96k / 192k) without dividing the clock (done that, but no space available) outside of the STM32 ?
And without any downsampling by the CPU.
Any ideas? Something I have overseen?
