I am developing a system composed of multiple STM32-based boards organized in a
layered architecture: six slave layers each with a nucelo f439zi perform data acquisition, while one master board still f439zi, manages synchronization and orchestration thought the timer signal, PWM output of channel 1 of TIM1 at 400khz: this signal is used to trigger the ADC of different MCU to have a synchronization across all system of sampling time.
The power supply is Distributed centrally by the Master Layer with a DCDC converter (or lab dc power supply) through ribbon connectors, total length of 80cm :i actually have 3 power supply over a 16 pin ribbon cable: 3.3V, 5V, 29.5V.
The PWM generated by the master layer has a separate Ribbon connector 14wires : 1 wire for PWM signal, 13wires to GND, that reaches all the 6 slaves boards
Nucleo are connected to the 5V rail in parallel, and after connecting each layer of the system, VCC drops around 70mV for each layer, even the lab dc supply shows always the 5V, is actually less (like 4.5V after all)
4 out of 6 SLVE layers fails- increasing the current consumption of the single MCU by 200-300mA, and permanently damage them.
the GND difference between the two more distant points is 10mV
My hypothesis it that The PWM signal I generate interferes with the boards with each other because - even the power supply is one - considering i have a layer each 10cm, from parasitic effects, locally the power supply looks different.
Will a optocoupler before each nucleo solve the problem, giving and electrical isolation - or - is it feasible to use a CAN protocol and implement a synchronization of the ADCs as now with the timer PWM?
NOTE:
I want to use GPIO ports (input - output) as basic flags and ack across those layers to flag the begin or the end of sampling, or minimal inter-board communication: SHOULD i have resistor between those GPIO?
ROSE is the schematic for slaves boards
MAKI is the schematic of master
