RM0377 MIFRST - what is E2 and what is IDDQ mode?

[waclawek.jan]

MIFEN explanation would use some rewording, too...

JW

[waclawek.jan]

Unrelated, but I don't want to inflate the number of threads: obviously copy/paste error, description of this bit should not talk about NVM:

JW

[waclawek.jan]

One more, again unrelated:

This is incorrect reference - the backup/RTC domain reset is described in chapter 7.1.3 RTC and backup registers reset .

JW

[Amel NASRI]

Hi @Community member​ ,

I come back to this old discussion to confirm that following updates will be applied in RM0377:

• MIFRST bitfield description in RCC_AHBRSTR:
  • Error: E2 and IDDQ are not defined.
  • This will be replaced by "This reset can be activated only when the NVM is in power-down mode."
  • Same sentence will be removed from MIFEN description
• SRAMSMEN bitfield description in RCC_AHBSMENR:
  • NVM should be replaced by SRAM
• The note in the description of RCC_CSR:
  • Error: Wrong reference for “RTC domain reset�?
  • It should refer to section 7.1.3 (RTC and backup registers reset) instead of “Section 6.1.2)

Thanks for your continuous help to improve our deliveries.

-Amel

[waclawek.jan]

Thanks, Amel.

Jan

@Amel NASRI​